Efficient Power Conversion Corporation

International Rectifier Corporation

Infineon Technologies Americas Corp.

Jianjun Cao

Robert A Beach

Alexander Lidow

Alana Nakata

Guangyuan Zhao

Robert Strittmatter

Kyle A Spring

Yanping Ma

Seshadri Kolluri

Chunhua Zhou

Ming-Kun Chiang

Jiali Cao

Guang Yuan Zhao

Fang Chang Liu

Agus Jauhar

Timothy Donald Henson

Zhi He

Michael A Briere

Johan Tjeerd Strydom

Paul Bridger

Paul Harvey

Muskan Sharma

Fang-Chang Liu

Daniel Marvin Kinzer

Michael Andrew De Rooij

Thomas Herman

Robert J Montgomery

David C Reusch

Sadiki Jordan

David Kent

Zhikai Tang

Yoganand Saripalli

Michael A De Rooji

Ajit Dubhashi

Naresh Thapar

Hugo R Burke

Edward Lee

Harold E Davis

Kenneth Wagers

Stephen L Colino

Jorge Cerezo

Ying Xiao

Qun Zhao

Nazanin Amani

Dave Kent

Jie Hu

Wen-Chia Liao

Guang Yuang Zhao

Gordon Stecklein

An integrated gate overvoltage protection circuit for protecting the gate of a main field effect transistor (FET). The gate protection circuit includes a blocking FET and a discharge FET connected between the gate and the drain of the main FET. The gate overvoltage protection circuit is configured to turn on both the first FET and the second FET in the event of a fault condition, such that charge from the gate of the main FET is discharged through the first FET and the second FET to the drain of the main FET, thereby protecting the gate of the main FET.

Integrated circuit for gate overvoltage protection of power devices

An integrated circuit which includes a GaN FET and a metal-insulator-metal capacitor. The capacitor is fully integrated with a lateral GaN process flow, i.e., the same gate metal layer, field plate metal layer and dielectric layer of the GaN FET are also used to form the bottom plate, insulator and top plate of the capacitor. The top plate is contacted by a conductive via, which extends through the top plate. To increase the voltage breakdown capability of the capacitor of the integrated circuit, a portion of the gate metal layer is formed in the shape of a ring around the conductive via.

Gate metal-insulator-field plate metal integrated circuit capacitor and method of forming the same

A gallium nitride (GaN) transistor which includes multiple insulator semiconductor interface regions. Two or more first insulator segments and two or more second insulator segments are positioned between the gate and drain contacts and interleaved together. At least one first insulator segment is nearer to the gate contact than the second insulator segments. At least one second insulator segment is nearer to the drain contact than the first insulator segments. The first and second insulators are chosen such that a net electron donor density above the channel under the first insulator segments is lower than a net electron density above the channel under the second insulator segments. The first insulator segments reduce gate leakage and electric fields near the gate that cause high gate-drain charge. The second insulator segments reduce electric fields near the drain contact and provide a high density of charge in the channel for reduced on-resistance.

Field plate structures with patterned surface passivation layers and methods for manufacturing thereof

A lateral power semiconductor device with a metal interconnect layout for low on-resistance. The metal interconnect layout includes first, second, and third metal layers, each of which include source bars and drain bars. Source bars in the first, second, and third metal layers are electrically connected. Drain bars in the first, second, and third metal layers are electrically connected. In one embodiment, the first and second metal layers are parallel, and the third metal layer is perpendicular to the first and second metal layers. In another embodiment, the first and third metal layer are parallel, and the second metal layer is perpendicular to the first and third metal layers. A nonconductive layer ensures solder bumps electrically connect to only source bars or only drain bars. As a result, a plurality of available pathways exists and enables current to take any of the plurality of available pathways.

Lateral power device with reduced on-resistance

An integrated circuit that includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Integrated circuit with multiple gallium nitride transistor sets

An enhancement-mode transistor gate structure which includes a spacer layer of GaN disposed above a barrier layer, a first layer of pGaN above the spacer layer, an etch stop layer of p-type Al-containing column III-V material, for example, pAlGaN or pAlInGaN, disposed above the first p-GaN layer, and a second p-GaN layer, having a greater thickness than the first p-GaN layer, disposed over the etch stop layer. The etch stop layer minimizes damage to the underlying barrier layer during gate etching steps, and improves GaN spacer thickness uniformity.

Enhancement-mode GaN transistor with selective and nonselective etch layers for improved uniformity in GaN spacer thickness

An integrated DC-DC converter device includes a plurality of GaN transistor sets. A first set of the plurality of GaN transistor sets includes transistors with a first drain-to-source distance, and wherein a second of the plurality of GaN transistor sets includes transistors with a second drain-to-source distance that is greater than the first drain-to-source distance.

Integrated gallium nitride based DC-DC converter

Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

Semiconductor devices with back surface isolation

A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.

GaN transistors with polysilicon layers used for creating additional components

An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self-aligned ledges that extend toward the source contact and drain contact, respectively.

Gate with self-aligned ledge for enhancement mode GaN transistors

A gallium nitride (GaN) transistor which includes two or more insulator semiconductor interface regions (insulators). A first insulator disposed between the gate and drain (near the gate) minimizes the gate leakage and fields near the gate that cause high gate-drain charge (Q). A second insulator (or multiple insulators), disposed between the first insulator and the drain, minimizes electric fields at the drain contact and provides a high density of charge in the channel for low on-resistance.

Multi-step surface passivation structures and methods for fabricating same

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.

Flip chip interconnection with reduced current density

An enhancement-mode GaN transistor with reduced gate leakage current between a gate contact and a 2DEG region and a method for manufacturing the same. The enhancement-mode GaN transistor including a GaN layer, a barrier layer disposed on the GaN layer with a 2DEG region formed at an interface between the GaN layer and the barrier layer, and source contact and drain contacts disposed on the barrier layer. The GaN transistor further includes a p-type gate material formed above the barrier layer and between the source and drain contacts and a gate metal disposed on the p-type gate material, with wherein the p-type gate material including comprises a pair of self- aligned ledges that extend toward the source contact and drain contact, respectively.

Gate with self-aligned ledged for enhancement mode GaN transistors

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Torrance, CA, United States of America

Jianjun Cao