Intel Corporation

Huawei Technologies Co., Limited

Jiangqi He

Xiang Yin Zeng

Daoqiang Lu

Yuan-Liang Li

Dong Zhong

Hyunjun Kim

Wei Shi

Qing A Zhou

Dong-Ho Han

Joong-Ho Kim

David Gregory Figueroa

Jiamiao Tang

Ping Sun

BaoShu Xu

John J Tang

Robert L Sankman

Cengiz Ahmet Palanduz

Jung S Kang

Tae Hong Kim

Ding Hai

Guizhen Zheng

Kai Xiao

Xiang Li

Hao-Han Hsu

Sriram Muthukumar

Mostafa Naguib Abdulla

Yiqun Bai

Yun Ling

Michael Walk

Bin Zou

Gong Ouyang

Edward A Zarbock

Guotao Wang

Farzaneh Yahyaei-moayyed

Wei Shen

John Tang

Hongfei Yan

Lu-Vong T Phan

Chris Baldwin

Rockwell M Hsu

Chunlei Guo

Ming Dong Cui

Gregory V Christensen

Wei Xu

Yan Guo

Zipeng Luo

Tianming Zhang

Daoqiang (Daniel) Lu

Jiamiao(John) Tang

A chip-to-chip process variation aware power efficiency optimization method that includes determining, using an adaptive voltage scaling (AVS) module of a processing unit in a system, an optimal voltage identification (VID) based on chip process variation. The method outputs the optimal VID from the AVS module to a voltage regulator of the system. The method adjusts a direct current (DC) load line setting based on the optimal VID of the processing unit in the system. The method regulates, using the voltage regulator of the system, a voltage supplied to the processing unit based on the DC load line setting.

Chip-process-variation-aware power-efficiency optimization

A package including a package substrate; an interposer electrically coupled to the package substrate and including a metal layer; a die including an integrated voltage regulator and electrically coupled to the interposer by solder features; and an inductor formed by a magnetic material disposed between two of the solder features electrically coupled to each other by a portion of the metal layer of the interposer, the inductor electrically coupled to the integrated voltage regulator.

Embedded thin-film magnetic inductor design for integrated voltage regulator (IVR) applications

A method and device for temperature measurement of a processor is disclosed. A temperature-sensing circuit of the processor may have an associated resonance frequency, wherein the resonance frequency depends on a temperature of the temperature-sensing circuit. A temperature of the temperature-sensing circuit may be determined by determining the resonance frequency of the temperature-sensing circuit.

Technologies for temperature measurement of a processor

In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

Shielding a connector to reduce interference

Methods and apparatus relating to self-referencing pins are described. In one embodiment, a pin electrically couples a first agent to a second agent. The pin includes two or more portions that are at least partially separated by an insulator, e.g., to improve crosstalk performance. Other embodiments are also disclosed and claimed.

Self referencing pin

Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed.

Multi-chip assembly with optically coupled die

In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed.

Forming compliant contact pads for semiconductor packages

An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.

Integrated capacitors in package-level structures, processes of making same, and systems containing same

A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security.

Substrate with raised edge pads

A spiral inductor is disposed above a substrate that includes two different materials. A dielectric film is the first material that provides structural integrity for the substrate. A second dielectric is the second material that provides a low dielectric-constant (low-K) material closest to the spiral inductor coil. A process of forming the spiral inductor includes patterning the substrate to allow a recess as a receptacle for the second dielectric, followed by forming the spiral inductor mostly above the second dielectric.

Packaged spiral inductor structures, processes of making same, and systems containing same

A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a mating surface become parallel and adjacent. The process includes placing a first die in a first die recess of the first heat spreader, and placing a second die in a second die recess in the second heat spreader. The process includes reflowing thermal interface material between each die and respective heat spreader. Thereafter, the process includes separating the first heat spreader and the second heat spreader. A package is achieved by the process, with reduced thicknesses. The package can be disposed onto a mounting substrate. The package can be assembled into a computing system.

Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and systems containing same

In one embodiment, the present invention includes a semiconductor package with lossy material inserts. The lossy material inserts may reduce electronic noise such as package resonance. Other embodiments are described and claimed.

Substrate with lossy material insert

A package may include a substrate provided with noise absorbing material. The noise absorbing material may absorb noise from a signal path in the substrate to prevent the noise from reaching other signals or signal paths.

Package level noise isolation

Growing community of inventors

Gilbert, AZ, United States of America

Jiangqi He