Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

National Yang Ming Chiao Tung University

Quanta Display Inc.

Jian-Zhi Huang

Chih-I Wu

I-Chih Ni

Yun-Hsuan Hsu

Han-Ping D Shieh

Ya-Ting Chang

Ke-Wei Su

Yi-Ting Wang

Chia-Feng Yang

Chung-Shi Chiang

Ya-Chin Liang

Chia-Ying Lin

Chia-Chi Ho

Hsien-Ming Chen

Yen-Chung Lin

Jiun-Shiau Wang

Jin-Bin Yang

Pei-Ming Chen

Yen-Lin Wei

An-Chih Wang

A semiconductor structure includes a semiconductor substrate, a gate structure, a source/drain structure, a contact, a dielectric layer, and a metal line. The gate structure is on the semiconductor substrate. The source/drain structure is adjacent to the gate structure. The contact lands on the source/drain structure. The dielectric layer spas the contact and the gate structure. The metal line extends through the dielectric layer to the contact. The metal line includes a liner over the contact, a magnetic layer over the liner, a graphene layer over the magnetic layer, and a filling metal over the graphene layer. The magnetic layer has a greater permeability coefficient than the filling metal.

Semiconductor device and method for forming the same

A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.

A method for forming an integrated circuit device is provided. The method includes forming a transistor over a frontside of a substrate; forming an interconnect structure over the transistor; depositing a first transition metal layer over the interconnect structure; performing a plasma treatment to turn the first transition metal layer into a first transition metal dichalcogenide layer; forming a dielectric layer over the first transition metal dichalcogenide layer; forming a first gate electrode over the dielectric layer and a first portion of the first transition metal dichalcogenide layer; and forming a first source contact and a first drain contact respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer, the first portion of the first transition metal dichalcogenide layer being between the second and third portions of the first transition metal dichalcogenide layers.

Integrated circuit device and method for forming the same

A method includes loading a wafer into a processing chamber, wherein the processing chamber is wound by a coil, and the coil is coupled to an RF system; supplying an aromatic hydrocarbon precursor into the processing chamber; after supplying the aromatic hydrocarbon precursor, turning on an RF power of the RF system to decompose the aromatic hydrocarbon precursor into active radicals and cyclize the active radicals into a graphene layer over a metal layer on the wafer; and after an entirety of the metal layer being covered by the graphene layer, turning off the RF power of the RF system to stop forming the graphene layer.

Deposition system and method using the same

In some embodiments, in a method, a netlist is received. The netlist comprises a subcircuit that comprises a device and a rule check module. The rule check module specifies a plurality of terminals of the device subject to an operating space, and at least one parameter that controls a non-rectangular boundary of the operating space. The netlist is simulated to obtain simulation data associated with the terminals of the device. The operating space that has the non-rectangular boundary is formed by using the at least one parameter. The simulation data is checked against the operating space. A situation in which the checked simulation data does not fall within the operating space is reflected.

Circuit simulation with rule check for device

An active TFT circuit structure with current scaling function is disclosed, which includes a current source, a data line, a scan line, a direct current voltage source, capacitors and four transistors, wherein the capacitors form a cascade structure. During the ON-state, the two of the transistors are turn-on based on the voltage provided by the scan line, so that the data current provided by the current source flows through the data line-and the transistor which is one of the opened transistors, thereby arriving an emitting light element and the transistor connected to the emitting light element. When the pixel circuit changes from ON- to OFF-state, the voltage of the node between the storage capacitors reduces due to the feed-through effect of one of storage capacitor, thereby reducing the driving current of the emitting light element. Therefore, it can be achieved the current scaling function.

Current-scaling active thin film transistor circuit structure for pixel of display device

Growing community of inventors

Hsinchu, Taiwan

Jian-Zhi Huang