St Assembly Test Services Inc.

Jian Jun Li

Il Kwon Shim

Dario S Filoteo, Jr

Kwee Lan Tan

Guruprasad G Badakere

Sheila Alvarez

A method of manufacturing an integrated circuit package includes: forming a substrate including: forming a core layer, and forming vias in the core layer; forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Integrated circuit package with open substrate and method of manufacturing thereof

A method of manufacturing an integrated circuit package includes: forming a substrate that includes: forming a core layer, forming vias in the core layer, and forming a conductive layer having a predetermined thickness on the core layer and having substantially twice the predetermined thickness in the vias; and forming connections between an integrated circuit die and the conductive layer.

Integrated circuit package with open substrate

An integrated circuit package comprises a substrate including a core layer with a through opening and vias. A first conductive layer is on the core layer covering the through opening and a second conductive layer is on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

A method for manufacturing an integrated circuit package comprises forming a substrate by forming a core layer with a through opening and vias. A first conductive layer is formed on the core layer covering the through opening and a second conductive layer is formed on the core layer opposite the first conductive layer in the through opening and in the vias contacting the first conductive layer. An integrated circuit die is bonded to the second conductive layer and in the through opening. Connections are formed between the integrated circuit die and the second conductive layer, and the integrated circuit die and the connections are encapsulated.

Chip scale package with open substrate

An integrated circuit package is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Integrated circuit package

An integrated circuit package, and manufacturing method therefor, is provided. A substrate is provided having solder openings therein and a conductive layer thereon. The conductive layer is processed to form a plurality of pads over the solder openings in the substrate. A mask is formed over the plurality of pads and openings formed in the mask over at least two pads of the plurality of pads. An integrated circuit die is bonded over the substrate using a conductive adhesive where the conductive adhesive is placed in the openings in conductive contact with at least two pads of the plurality of pads.

Integrated circuit package and manufacturing method therefor with unique interconnector

A new method is provided for the creation of high-accuracy and low-accuracy openings overlying points of electrical access over the surface of a semiconductor device supporting substrate. Openings are first created for access to the substrate followed by copper plating and then patterning of the plated layer of copper, creating the interconnect metal over the surface of the substrate. A first solder mask is coated over the surface of the substrate, this first solder mask must be provided with a first array of low-accuracy openings for electrical access there-through for the placement of contact balls. The first openings can be created using conventional film artwork since low accuracy is required for the contact ball openings, resulting in a low-cost process for the creation of the first openings. A second solder mask is next coated over the surface of the first solder mask. Through this second solder mask is created a second array of high-accuracy second openings that provide access to solder bumps using methods of laser ablation, resulting in a low-throughput process which however is only applied to create access to solder bumps.

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Singapore, Singapore

Jian Jun Li