Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Technoloiges LLC

Jiahui Yuan

Yingda Dong

Yi Song

Abu Naser Zainuddin

Deepanshu Dutta

Yu-Chung Lien

Liang Li

Sarath Chandran Puthenthermadam

Xiang Yang

Liang Pang

Lito De La Rama

Ramy Nashed Bassely Said

Charles S Kwong

Jian Feng Chen

Jayavel Pachamuthu

Abhijith Prakash

Jiacen Guo

Xiaochen Zhu

Dengtao Zhao

Toru Miwa

Wei Zhao

Yanjie Wang

Ming Wang

Raghuveer S Makala

Yanli Zhang

James Fitzpatrick

Ching-Huang Lu

Senaka Kanakamedala

Towhidur Razzak

Longju Liu

Johann Alsmeier

Nian Niles Yang

Christopher John Petti

Dana Lee

Huai-Yuan Tseng

Niles Yang

Bo Lei

Mark Shlick

Ravi J Kumar

Loc Tu

Ke Zhang

Ohwon Kwon

Parth Amin

Xuan Tian

Sai Gautham Thoppa

Fanqi Wu

Yihang Liu

Jingjian Ren

Vishwanath Basavaegowda Shanthakumar

Go Shoji

Albert Chen

Masaaki Higashitani

Wei Zhang

Ming Hsi Wang

Henry Chin

Jun Wan

Mohan Dunga

Hong-Yan Chen

Xinde Hu

Grishma Shah

Anubhav Khandelwal

Shih-Chung Lee

Shinsuke Yada

Guirong Liang

Muhammad Masuduzzaman

Yongke Sun

Pao-Ling Koh

Dongxiang Liao

Tomer Eliash

Xue Bai Pitner

Wei Cao

Kou Tei

Zhiping Zhang

Hiroyuki Mizukoshi

Sujjatul Islam

Wenzhou Chen

Qianqian Yu

Akira Okada

Chin-Yi Chen

Lanlan Gu

Jia Li

Kazuki Isozumi

Shemmer Choresh

Zhenni Wan

Vincent Yin

Keyur Payak

Dong-Il Moon

Feng Gao

Yichen Wang

Bin Wu

Jie Liu

Kai Kirk

Xue Qing Cai

Charles Kwong

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means ramps up and applies a read voltage to unselected ones of the word lines while applying verification pulses of program verify voltages each associated with one of the plurality of data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the verify voltages associated with the plurality of data states targeted during a program-verify operation. The control means delays ramping of at least one of the selected ones of the word lines and the unselected ones of the word lines by a predetermined period of time in response to the memory apparatus operating in a predetermined mode.

Program verify word line ramping delay for lower current consumption mode

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.

Variable read method for read time performance improvement of non-volatile memory

An apparatus includes a memory structure including non-volatile memory cells, and a control circuit coupled to the memory cell. The control circuit configured to first read a block of non-volatile memory cells using a first plurality of read levels, determine that the first read fails to successfully read the block of non-volatile memory cells, second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels, determine that the second read successfully reads the block of non-volatile memory cells, estimate that the first read failed because of data retention or read disturb, and erase and re-write data to the block of non-volatile memory cells.

Apparatus and methods for read retry with conditional data refresh

A memory system implemented on one or more die includes a power input line for the one or more die, a current detection circuit connected to the power input line such that the current detection circuit is configured to indicate whether current at the power input is greater than a reference current, and a control circuit connected to the power input line and the current detection circuit. The control circuit is also connected to a non-volatile memory structure comprising a plurality of non-volatile memory cells. The control circuit is configured to sense data from the non-volatile memory structure including lowering a voltage used during the sensing in response to the current detection circuit indicating that current at the power input line is greater than the reference current.

Non-volatile memory with current detection circuit

A non-volatile memory is configured to transition memory cells from programmed data states with the higher ranges of threshold voltages to programmed data states with the lower ranges of threshold voltages without the transitioning the memory cells to the erased data state.

Non-volatile memory with decline state operation

A non-volatile memory system tests for a voltage leak in any of multiple planes using a voltage being ramped up on selected word lines in the multiple planes. If no voltage leak is detected, then the system concurrently programs data into memory cells connected to the selected word lines in the multiple planes. If a voltage leak is detected in any of the planes, then the system separately tests each plane for the voltage leak at its respective selected word line in order to determine which plane is the source of the voltage leak, and then concurrently programs data into memory cells connected to the selected word lines in planes without the detected voltage leak while isolating the plane with the detected voltage leak.

Non-volatile memory with neighbor plane program disturb avoidance

A duration of a program pulse used to program non-volatile memory cells such as NAND may be increased responsive to a programming failure using a shorter duration program pulse. The duration of at least one program pulse may be increased for at least one group of memory cells in response to a failure to program a group using a default program pulse duration. The group that experiences the increased duration program pulse may be the same group for which the program operation failed using the shorter program pulse or may be a different group than the group for which the program operation failed using the shorter program pulse.

Program pulse duration increase for NAND program failure

While programming a first set of memory cells, a non-volatile memory apparatus determines an initial magnitude of a programming signal for a second set of memory cells based on testing during the programming of the first set of memory cells. The testing comprises sensing at a first test voltage level and sensing at a second test voltage level without apply a voltage spike between the two sensing operation. Removing the voltage spike results in a performance increase (i.e. faster programming speed) and as well as a decrease in power usage.

Non-volatile memory with efficient setting of initial program voltage

To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.

Separate peak current checkpoints for closed and open block read ICC countermeasures in NAND memory

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Three-dimensional memory device with source line isolation and method of making the same

A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.

Non-volatile memory that dynamically reduces the number of bits of data stored per memory cell

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

Early program termination with adaptive temperature compensation

Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

Memory program-verify with adaptive sense time based on row location

Technology for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

Open block read ICC reduction

A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

Non-volatile memory with smart control of overdrive voltage

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Fremont, CA, United States of America

Jiahui Yuan