Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Sandisk Technoloiges LLC

Jiahui Yuan

Yingda Dong

Yi Song

Deepanshu Dutta

Abu Naser Zainuddin

Yu-Chung Lien

Liang Pang

Sarath Chandran Puthenthermadam

Xiang Yang

Liang Li

Charles S Kwong

Jian Feng Chen

Jayavel Pachamuthu

Abhijith Prakash

Ramy Nashed Bassely Said

Lito De La Rama

Dengtao Zhao

Wei Zhao

Jiacen Guo

Yanjie Wang

Xiaochen Zhu

Raghuveer S Makala

Yanli Zhang

James Fitzpatrick

Ching-Huang Lu

Senaka Kanakamedala

Toru Miwa

Towhidur Razzak

Longju Liu

Johann Alsmeier

Nian Niles Yang

Christopher John Petti

Dana Lee

Huai-Yuan Tseng

Niles Yang

Bo Lei

Ravi J Kumar

Ke Zhang

Ohwon Kwon

Xuan Tian

Fanqi Wu

Ming Wang

Yihang Liu

Jingjian Ren

Go Shoji

Masaaki Higashitani

Ming Hsi Wang

Henry Chin

Jun Wan

Mohan Dunga

Xinde Hu

Hong-Yan Chen

Grishma Shah

Shih-Chung Lee

Shinsuke Yada

Mark Shlick

Guirong Liang

Muhammad Masuduzzaman

Loc Tu

Pao-Ling Koh

Dongxiang Liao

Yongke Sun

Tomer Eliash

Xue Bai Pitner

Kou Tei

Parth Amin

Wenzhou Chen

Zhiping Zhang

Sujjatul Islam

Hiroyuki Mizukoshi

Qianqian Yu

Lanlan Gu

Chin-Yi Chen

Zhenni Wan

Shemmer Choresh

Sai Gautham Thoppa

Jia Li

Vincent Yin

Keyur Payak

Kazuki Isozumi

Bin Wu

Feng Gao

Dong-Il Moon

Vishwanath Basavaegowda Shanthakumar

Jie Liu

Xue Qing Cai

Kai Kirk

Albert Chen

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells and a second set of the non-volatile memory cells in a plurality of program loops, determine that at least one of the first set of the non-volatile memory cells and the second set of the non-volatile memory cells verification to a programmed state in a first number of program loops, and compare a difference between the first number of program loops and the second number of program loops to an adaptive maximum loop delta limit. The adaptive maximum loop delta limit varies as a function of temperature.

Early program termination with adaptive temperature compensation

Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.

Memory program-verify with adaptive sense time based on row location

Technology for a storage system that reduces the Icc during open block reads. A lower than nominal voltage may be applied to the bit lines during open block reads, which reduces Icc. A nominal bit line voltage may be used during closed block reads. The lower than nominal bit line voltage may be combined with using a lower than nominal read pass voltage (Vread) to unprogrammed word lines during the open block read. The lower than nominal Vread has a lower magnitude than a nominal Vread used during a closed block read. Combining the lower than nominal bit line voltage with the lower than nominal Vread to unprogrammed word lines further reduces Icc during open block reads. The ramp rate of Vread may be relaxed (made slower) during at least some open block reads in combination with the lower than nominal bit line voltage.

Open block read ICC reduction

A non-volatile memory system detects a memory operation failure. In response to the memory operation failure, the system determines whether adjusting an overdrive voltage applied to a word line avoids the memory operation failure. If adjusting the overdrive voltage applied to the word line avoids the memory operation failure, then future memory operations are performed by applying the adjusted overdrive voltage to the word line.

Non-volatile memory with smart control of overdrive voltage

The memory device includes a memory block with an array of memory cells that are arranged in word lines. The word lines are in electrical communication with respective word line drivers and switches. Control circuitry is configured to program the memory cells of a selected word line in a programming operation during which the control circuitry applies an elevated voltage to the selected word line and receives a command to suspend the programming operation. With the word line switch associated with the selected word line turned on, the control circuitry ramps the selected word line from the elevated voltage to a reduced gate holding voltage and then turn the word line switch associated with the selected word line off to electrically isolate the selected word line from the associated word line driver so that the selected word line remains at the gate holding voltage until the programming operation resumes.

Suspend-resume-go techniques for memory devices

An apparatus is provided that includes a plurality of non-volatile memory cells, a charge pump circuit configured to receive a clock signal and provide a plurality of voltages to the non-volatile memory cells, and a control circuit coupled to the non-volatile memory cells and the charge pump circuit. The control circuit is configured to reduce a current consumed by the apparatus by selectively reducing a clock rate of the clock signal depending on a memory operation being performed on the non-volatile memory cells.

Apparatus and method for selectively reducing charge pump speed during erase operations

A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

Non-volatile memory with lower current program-verify

A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.

Non-volatile memory with efficient testing

A non-volatile memory system is configured to program non-volatile memory cells by applying doses of programming to the memory cells and performing a program-verify operation following each dose of programming. Each dose of programming and the corresponding program-verify operation following the dose of programming is referred to as a program loop. The program-verify operation comprises applying a verify reference voltage to a selected word line and applying an overdrive voltage to unselected word lines. To reduce the amount of current used, the memory system includes a loop dependent reduction in the ramp-up rate of the overdrive voltage applied to unselected word lines during program-verify.

Non-volatile memory with loop dependant ramp-up rate

To reduce Icc spikes during the operation of a non-volatile memory device, a distributed temperature sensing system individually monitors each plane of a memory die during memory operations. Icc levels during a memory operation are temperature dependent. By monitoring the temperature of the individual memory planes during an operation, the bias levels for performing the operation can be changed during the course of that operation in order to reduce Icc spikes during the operation. For example, during a write operation if the temperature increase of a plane exceeds a threshold during earlier programming loops, the bias conditions, such as word line or bit line bias voltages, can be altered for later programming loops of the write operation.

Distributed temperature sensing scheme to suppress peak Icc in non-volatile memories

Technology for managing non-volatile memory. A bitmap may be maintained in NAND memory cells. The bits in the bitmap map to an address (e.g., PBA) in the NAND memory cells. Each bit has either a first value to indicate that the corresponding address stores valid data or a second value to indicate that the corresponding address does not store value data. Garbage collection may be performed based on the bitmap. Bit-level memory operations are performed to maintain the bitmap. Bit-level erase may be performed to erase a memory cell to have a value that indicates a valid/invalid status. The bitmap may contain unencoded data. In one aspect, a one's complement to the bitmap is stored in the NAND memory cells. The one's complement has opposite values as the regular bitmap. The system may compare the values in the regular bitmap and the one's complement bitmap for data integrity.

Non-volatile memory bitmap for garbage collection

A memory device includes a horizontal source layer which is laterally separated into laterally isolated portions located in adjacent memory blocks by a dielectric backside trench fill structure or a source isolation dielectric structure.

Three-dimensional memory device with source line isolation and method of making the same

A non-volatile memory system is configured to permanently erase a single file from a block of non-volatile memory cells. That block is storing programmed data including the single file to be erased and other programmed data. The single file is erased from the block such that the other programmed data in the block is not moved or otherwise disturbed.

Non-volatile memory with secure erase

An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

Apparatus and methods for smart verify with adaptive voltage offset

To reduce data disturbs and lower current requirements of a 3D NAND memory die, a multi-block plane of non-volatile memory cells has its source line separated into multiple source line regions by introduction of isolation trenches. The plane structure for the NAND memory is maintained, but is broken into multi-block sub-planes, each with an independently biasable source line.

Non-volatile memory with sub-planes having individually biasable source lines

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Fremont, CA, United States of America

Jiahui Yuan