Taiwan Semiconductor Manufacturing Comp. Ltd.

Ji-Yin Tsai

Clement Hsingjen Wann

Chih-Hsin Ko

Jiun-Ming Kuo

Che-Lun Chang

Yao-Tsung Huang

Yee-Chia Yeo

Chii-Horng Li

Pei-Ren Jeng

Kei-Wei Chen

Hsin-Chieh Huang

Yuan-Ching Peng

Ming-Yuan Wu

Ming-Jie Huang

Yu-Wen Wang

Che-Yuan Hsu

Jung-Jen Chen

Yu-Lin Tsai

Shiao-Shin Cheng

Cheng-Hsien Wu

Chao-Ching Cheng

Da-Wen Lin

Yi-Fang Pai

Jeng-Wei Yu

Meng-Ku Chen

Hung-Ju Chou

Min Jiao

The present disclosure provide a method that includes receiving a substrate having a semiconductor surface of a first semiconductor material; forming an APT feature in the substrate; performing a prebaking process to the substrate with a first temperature T; epitaxially growing an undoped semiconductor layer of the first semiconductor layer and a first thickness ton the substrate at a second temperature T; epitaxially growing a semiconductor layer stack over the undoped semiconductor layer at a third temperature Tless than T, wherein the semiconductor layer stack includes first semiconductor layers and second semiconductor layers stacked vertically in an alternating configuration; patterning the semiconductor substrate, and the semiconductor layer stack to form a trench, thereby defining an active region being adjacent the trench; forming an isolation feature in the trench; selectively removing the second semiconductor layers; and forming a gate structure wrapping around each of the first semiconductor layers.

Method and multi-channel devices with anti-punch-through features

A first layer is formed over a substrate; a second layer is formed over the first layer; and a third layer is formed over the second layer. The first and third layers each have a first semiconductor element; the second layer has a second semiconductor element different from the first semiconductor element. The second layer has the second semiconductor element at a first concentration in a first region and at a second concentration in a second region of the second layer. A source/drain trench is formed in a region of the stack to expose side surfaces of the layers. A first portion of the second layer is removed from the exposed side surface to form a gap between the first and the third layers. A spacer is formed in the gap. A source/drain feature is formed in the source/drain trench and on a sidewall of the spacer.

Methods of forming of inner spacer structure using semiconductor material with variable germanium concentration

In an embodiment, a device includes: a substrate; a first semiconductor region extending from the substrate, the first semiconductor region including silicon; a second semiconductor region on the first semiconductor region, the second semiconductor region including silicon germanium, edge portions of the second semiconductor region having a first germanium concentration, a center portion of the second semiconductor region having a second germanium concentration less than the first germanium concentration; a gate stack on the second semiconductor region; and source and drain regions in the second semiconductor region, the source and drain regions being adjacent the gate stack.

Semiconductor device and method

A method includes forming a semiconductor fin protruding higher than a top surface of an isolation region. The semiconductor fin overlaps a semiconductor strip, and the semiconductor strip contacts the isolation region. The method further includes forming a gate stack on a sidewall and a top surface of a first portion of the semiconductor fin, and etching the semiconductor fin and the semiconductor strip to form a trench. The trench has an upper portion in the semiconductor fin and a lower portion in the semiconductor strip. A semiconductor region is grown in the lower portion of the trench. Process gases used for growing the semiconductor region are free from both of n-type dopant-containing gases and p-type dopant-containing gases. A source/drain region is grown in the upper portion of the trench, wherein the source/drain region includes a p-type or an n-type dopant.

Method for forming an undoped region under a source/drain

Inner spacer structure and methods of forming such

A method includes forming a doped region on a top portion of a substrate, forming a first epitaxial layer over the substrate, forming a recess in the first epitaxial layer, the recess being aligned to the doped region, performing a surface clean treatment in the recess, the surface clean treatment includes: oxidizing surfaces of the recess to form an oxide layer in the recess, and removing the oxide layer from the surfaces of the recess, and forming a second epitaxial layer in the recess.

Fin field-effect transistor device and method

A method includes forming a gate stack over a semiconductor region, and recessing the semiconductor region to form a recess adjacent the gate stack. A silicon-containing semiconductor region is epitaxially grown in the recess to form a source/drain stressor. Arsenic is in-situ doped during the step of epitaxially growing the silicon-containing semiconductor region.

Silicon germanium source/drain regions

In-situ doping of arsenic for source and drain epitaxy

The invention relates to integrated circuit fabrication, and more particularly to a semiconductor device with an interfacial layer. An exemplary structure for a semiconductor device comprises a SiGesubstrate, wherein the x is greater than 0.4; a Si layer over the SiGesubstrate; and a gate structure disposed over the Si layer, wherein the gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion; wherein the dielectric portion comprises a layer of III-V material on the Si layer and a high-k dielectric layer adjacent to the electrode portion.

Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer

Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a channel region in a workpiece, and forming a source or drain region proximate the channel region. The source or drain region includes a contact resistance-lowering material layer comprising SiP, SiAs, or a silicide. The source or drain region also includes a channel-stressing material layer comprising SiCP or SiCAs.

Semiconductor devices and methods of manufacture thereof

Growing community of inventors

Zhudong, Taiwan

Ji-Yin Tsai