Samsung Electronics Co., Ltd.

Ji-Woon Im

Sang-Hoon Lee

Kyung-Hyun Kim

Hee-Sook Park

Ik-Soo Kim

Myoung-Bum Lee

Hyo-Jung Kim

Jong-Heun Lim

Seung-Mok Shin

Kyung-Tae Jang

Ju-Wan Kim

Tae-Jong Han

Il-Woo Kim

Koong-Hyun Nam

Ji-Youn Seo

Hyun-Yong Go

Sang-Gi An

Hyun-Gon Pyo

In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

Methods of manufacturing a vertical memory device

A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

Nonvolatile memory device and a method for fabricating the same

In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Vertical memory devices and methods of manufacturing the same

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Hwaseong-si, South Korea

Ji-Woon Im