United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Ji-Min Lin

Yi-Wei Chen

Chih-Chien Liu

Tsun-Min Cheng

Kun-Ju Li

Pin-Hong Chen

Chih-Chieh Tsai

Chun-Chieh Chiu

Tzu-Chieh Chen

Kai-Jiun Chang

Yi-An Huang

Yu-Lung Shih

Fu-Shou Tsai

Chia-Chen Wu

Yang-Ju Lu

Tzu-Hao Liu

Yong-Yi Lin

Po-Chih Wu

Ching-Yang Chuang

Chau-Chung Hou

Hsin-Jung Liu

Ang Chan

Chun-Han Chen

Jhih-Yuan Chen

Fu-Chun Hsiao

A fabricating method of transistors includes providing a substrate with numerous transistors thereon. Each of the transistors includes a gate structure. A gap is disposed between gate structures adjacent to each other. Later, a protective layer and a first dielectric layer are formed in sequence to cover the substrate and the transistors and to fill in the gap. Next, numerous buffering particles are formed to contact the first dielectric layer. The buffering particles do not contact each other. Subsequently, a second dielectric layer is formed to cover the buffering particles. After that, a first planarization process is performed to remove part of the first dielectric layer, part of the second dielectric layer and buffering particles by taking the protective layer as a stop layer, wherein a removing rate of the second dielectric layer is greater than a removing rate of the buffering particles during the first planarization process.

Fabricating method of transistors without dishing occurred during CMP process

A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.

Semiconductor device and method for fabricating the same

The present invention discloses a metal gate process. A sacrificial nitride layer is introduced during the fabrication of metal gates. The gate height can be well controlled by introducing the sacrificial nitride layer. Further, the particle fall-on problem can be effectively solved.

Method of manufacturing a semiconductor device

An alignment mark structure includes a dielectric layer. A trench is embedded in the dielectric layer. An alignment mark fills up the trench, wherein the alignment mark includes a metal layer covering the trench. A first material layer covers and contacts the metal layer. A second material layer covers and contacts the first material layer. A third material layer covers and contacts the second material layer. The first material layer, the second material layer, and the third material layer independently includes silicon nitride, silicon oxide, tantalum-containing material, aluminum-containing material, titanium-containing material, or a low-k dielectric having a dielectric constant smaller than 2.7, and a reflectance of the first material layer is larger than a reflectance of the second material layer, the reflectance of the second material layer is larger than a reflectance of the third material layer.

Alignment mark structure and method of fabricating the same

A method for fabricating semiconductor device includes the steps of: forming a titanium nitride (TiN) layer on a silicon layer; performing a first treatment process by reacting the TiN layer with dichlorosilane (DCS) to form a titanium silicon nitride (TiSiN) layer; forming a conductive layer on the TiSiN layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a metal silicon nitride layer on the silicon layer; forming a stress layer on the metal silicon nitride layer; performing a thermal treatment process; removing the stress layer; forming a conductive layer on the metal silicon nitride layer; and patterning the conductive layer, the metal silicon nitride layer, and the silicon layer to form a gate structure.

Method for fabricating semiconductor device

Growing community of inventors

Taichung, Taiwan

Ji-Min Lin