Samsung Electronics Co., Ltd.

Ji-Hye Yi

Yong-Ho Ha

Bong-jin Kuh

Ho Young Lee

Hwa-Sung Rhee

Beak-Hyung Cho

Hideki Horii

Chang-Wook Jeong

Myung-Sun Kim

Jun-Soo Bae

Jeong-Hee Park

Horii Hideki

Suk-Ho Joo

Myung-sun Kim

Seok-Jun Won

Gwan-Hyeob Koh

Jang-Eun Lee

Se-Ho Lee

Yoon-jong Song

Su-Jin Ahn

Soon-Oh Park

Young-Nam Hwang

Sung-lae Cho

Woo-Sik Kim

Kyung-Chang Ryoo

Tetsuji Ueno

Sang-Don Nam

Choong-Man Lee

Young-Tak Kim

Chul-Woong Lee

Su-Youn Lee

Kook-tae Kim

Ho-Sung Son

Jun-hyok Kong

Byung-seo Kim

Byeong-Ok Cho

Sung-Lae Cho

Jong-bong Park

Hion-suck Baik

Young-Soo Lim

Jung-Yun Won

Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.

Semiconductor device, method for fabricating the same, and memory system including the semiconductor device

Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Methods of forming phase-changeable memory devices including an adiabatic layer

Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

Semiconductor integrated circuit devices having different thickness silicon-germanium layers

A semiconductor device includes a gate insulator and a gate electrode stacked on a substrate, a source/drain pattern which fills a recess region formed at opposite sides adjacent to the gate electrode, the source/drain pattern being made of silicon-germanium doped with dopants and a metal germanosilicide layer disposed on the source/drain pattern. The metal germanosilicide layer is electrically connected to the source/drain pattern. Moreover, a proportion of germanium amount to the sum of the germanium amount and silicon amount in the metal germanosilicide layer is lower than that of germanium amount to the sum of the germanium amount and silicon amount in the source/drain pattern.

Semiconductor device including field effect transistor and method of forming the same

Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby

A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.

Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same

A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed.

Methods of manufacturing phase-changeable memory devices including upper and lower electrodes

In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.

Methods of fabrication of channel-stressed semiconductor devices

According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.

Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device

In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.

Method of manufacturing a semiconductor device

A phase-changeable memory device may include a substrate, an insulating layer on the substrate, first and second electrodes, and a pattern of a phase-changeable material between the first and second electrodes. More particularly, the insulating layer may have a hole therein, and the first electrode may be in the hole in the insulating layer. Moreover, portions of the second electrode may extend beyond an edge of the pattern of phase-changeable material. Related methods are also discussed.

Phase changeable memory device structures

Phase-changeable memory devices including phase-changeable materials on silicon nitride layers

Phase-changeable memory devices including an adiabatic layer

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Gyeonggi-do, South Korea

Ji-Hye Yi