Samsung Electronics Co., Ltd.

Ji-Hoon Lim

Bilal Ahmad Janjua

Seong-Jin Jang

Yong-Ho Cho

Venkataramana Gangasani

Ki-Heung Kim

Vivek Venkata Kalluru

Tae-Yoon Lee

Kwang-il Park

Taehui Na

June-Hong Park

Jungyu Lee

Jeong-Don Lim

Youngsun Min

Jongryul Kim

Surojit Sarkar

A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Nonvolatile memory device including temperature compensation circuit

A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Memory device for avoiding multi-turn on of memory cell during reading, and operating method thereof

A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Nonvolatile memory device including transfer element

A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

Memory devices and operation methods thereof

A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

Compensation circuit for generating read/program/erase voltage

A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

Level detector, internal voltage generator including level detector, and semiconductor memory device including internal voltage generator

A charge pump and method of operation are provided. The charge pump includes a first boosting unit configured to receive a pre-charge voltage and electrically charge a first MOS capacitor during a pre-charge period, and to boost a voltage of a connection node to a first output voltage during a boosting operation period, and a second boosting unit configured to receive the pre-charge voltage and electrically charge a second MOS capacitor during the pre-charge period, and to receive the first output voltage and boost a voltage of an output node to a second output voltage during the boosting operation period. Here, the pre-charge voltage is applied to electrically charge a parasitic capacitor during a parasitic capacitor charging period between the pre-charge period and the boosting operation period.

Charge pump and semiconductor device having the same

An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.

Growing community of inventors

Hwaseong-si, South Korea

Ji-Hoon Lim