Samsung Electronics Co., Ltd.

Ji-hong Ahn

Won-mo Park

Young-hun Park

Kyeong-tae Kim

Yun-seung Shin

Young-woo Seo

A semiconductor device having a closed step portion and a global step portion including an insulating layer having a planarized surface on the global step portion is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

Semiconductor device and a method of manufacture

A method for manufacturing a semiconductor device having a closed step portion and a global step portion including an insulating layer is provided. A dummy pattern is formed by forming an insulating layer on the global step portion and then patterning through a photolithography process. After forming the dummy pattern for compensating steps in the global step portion and between the closed step portion and the global step portion, a BPSG layer is formed on both the closed step portion and the global step portion, and then the BPSG layer is heat-treated to cause it to reflow. The BPSG layer as an insulating interlayer having a planarized surface. The improved planarization decreases the occurrence of notching and discontinuities in the succeeding metallization processes thereby enhancing the yield and electrical characteristics of the semiconductor device.

Method of manufacture of a semiconductor device

A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array region and peripheral circuit region. Also, a method for the semiconductor memory device is provided. Therefore, the conventional problem of degraded reliability of the conductive layer due to the step between the cell array region and peripheral circuit region, can be prevented. At the same time, the surface planarization of the peripheral circuit region can be attained.

Semiconductor memory device and a manufacturing method thereof

A method for manufacturing a capacitor of a highly integrated semiconductor memory device includes the steps of forming a conductive layer on the whole surface of a semiconductor substrate, forming a first material layer on the whole surface of the conductive layer, forming a polysilicon layer having hemispherical grains on the whole surface of the first material layer, forming a first material layer pattern by performing an etching on the first material layer, using the polysilicon layer as an etch-mask, partially removing the conductive layer by anisotropically etching the conductive layer, using the first material layer pattern as an etch-mask, defining the conductive layer into an individual unit cell, and removing the first material layer pattern. Since greater cell capacitance can be secured by a simple process, this method can be adopted to manufacturing semiconductor memory devices having packing densities up to 64 Mb and 256 Mb.

Method for manufacturing a capacitor of an integrated semiconductor

Disclosed are a semiconductor memory device and method for manufacturing the same. The method includes a process for manufacturing a capacitor performed by the steps of forming a first conductive layer on a semiconductor substrate, forming a first pattern composed of a 1st first-material layer on the first conductive layer, forming a first sidewall spacer composed of 1st second-material layer on the resultant structure, and etching the material layer under the first sidewall spacer, using the first sidewall spacer as an etch-mask. The semiconductor memory device thus manufactured can be highly integrated and is highly reliable.

Manufacturing method of a capacitor having a storage electrode whose

A semiconductor memory device and the method therefor is disclosed, in which memory cells having a transistor that has a source, a drain and a gate electrode, and a capacitor that has a storage electrode electrically connected to the source of the transistor, a dielectric layer and a plate electrode are formed on a semiconductor substrate in an orderly shape. In the memory cell, a covering layer is formed over the entire semiconductor region, except for an area defined to form the storage electrode, so as to be both insulated from the lower structure and the storage electrode. Accordingly, not only is prevented the phenomenon that data stored in a cell capacitor is destroyed by the residue of a polycrystal silicon layer, but also the surface thereof can be flattened in advance, limited only by the thickness of the polycrystal silicon layer.

Method of making a semiconductor memory device having improved

Method of making a semiconductor memory device

A high-density semiconductor memory device and its manufacturing method are disclosed. The device has a plurality of memory cells, each consisting of one transistor and one capacitor on a substrate in a matrix form. The capacitor, in contact with the source region of the transistor, consists of a storage electrode having a hollow cylindrical electrode with a wall of predetermined thickness, and a column electrode surrounded by the cylindrical electrode. The capacitor further comprises a plurality of bars, a base plate electrode connecting the cylindrical and column electrodes to each other, a dielectric layer coating the whole surface of the storage electrode, and a plate electrode formed on top of the dielectric layer. According to this invention, a greater capacitance may be obtained while avoiding current leakage and the disparity of cell capacitance problems involved with a conventional stack-type capacitor having a ringed structure.

High density semiconductor memory device (MBC cell)

In a highly integrated semiconductor memory device provided with memory cells in matrix form on a semiconductor substrate, each memory cell includes a transistor and a capacitor. The cell capacitor includes a storage electrode in contact with a source region of the transistor. This storage electrode has a plurality of irregularly shaped quasi-cylindrical holes formed therein at random locations. A dielectric film is coated on the whole surface of the storage electrode. Thus, storage electrodes having a large cell capacitance suitable for DRAM cells of highly integrated circuits can be achieved.

Highly integrated semiconductor memory device and the fabrication method

A method for manufacturing a villus-type capacitor of a semiconductor memory device formed by stacking a storage electrode, a dielectric film and a plate electrode on a semiconductor substrate further comprising the steps of forming a first conductive layer by depositing a conductive material on the semiconductor substrate; covering the first conductive layer with a second material having grains of a first material; selectively removing the second material using the grains of the first material as a mask; etching a predetermined portion of the first conductive layer using a grain pattern formed by removing the second material as a mask; removing the grain pattern; completing the formation of a storage electrode by defining into each unit cell the villus-formed first conductive layers on the surface of the device utillizing an etching process; forming the dielectric film over the surface of the storage electrode; and forming the plate electrode by depositing a second conductive layer over the dielectric film. The pillar-shaped storage electrode having dimensions below design rules and a buried bit line extend the capacitor's surface, resulting in an effective increase of capacitive area, and a corresponding increase in the cell capacitance.

Method for manufacturing a semiconductor device with villus-type

A method for manufacturing a capacitor of a highly integrated semiconductor memory device including a plurality of memory cells, each of which has a transistor and a capacitor. The method comprises the steps of forming an insulating layer for insulating the transistor, forming a contact hole to electrically connect to a source region by etching the insulating layer, sequentially forming a first polycrystalline silicon layer, an oxide layer, and a second polycrystalline silicon layer consisting of grains, exposing the second polycrystalline silicon layer to an oxide etchant, partially etching the oxide layer by the oxide etchant penetrating along the peripheries of the grains, anistropically etching the whole second polycrystalline silicon layer and, at the same time, the partial first polycrystalline silicon layer also, using the oxide layer being unaffected by the oxide etchant, as a mask, removing the oxide layer, forming a storage electrode by defining into cell units the first polycrystalline silicon layer, sequentially forming a dielectric film and a plate electrode formed of a third polycrystalline silicon layer over the resultant structure. Thus, the physical properties of the material itself is used without any specific conditions and unrestricted by limitation of minimum feature size. Furthermore, the process is greatly simplified and the effective capacitance of the cell capacitor is easily extended.

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Seoul, South Korea

Ji-hong Ahn