Taiwan Semiconductor Manufacturing Comp. Ltd.

United Microelectronics Corp.

United Semiconductor Corp.

Altasens, Inc.

United Semiconductor Circuit Corp.

Jhy-Jyi Sze

Dun-Nian Yaung

Yimin Huang

Ching-Chun Wang

Shyh-Fann Ting

Wei Chuang Wu

Jen-Cheng Liu

Feng-Chi Hung

Seiji Takahashi

Yen-Ting Chiang

Yu-Jen Wang

Yuichiro Yamashita

Chen-Jong Wang

Chun-Yuan Chen

Keng-Yu Chou

Tzu-Jui Wang

Alexander Kalnitsky

Hsiao-Hui Tseng

Shou-Gwo Wuu

Wei-Chieh Chiang

Kazuaki Hashimoto

Kuan-Chieh Huang

Tung-Ting Wu

Chien-Hsien Tseng

Chun-Hao Chuang

Yi-Shin Chu

Wen-Hau Wu

Hsiang-Lin Chen

Yin-Kai Liao

Sin-Yi Jiang

Yeur-Luen Tu

Chun-Wei Chang

Wei-Cheng Hsu

Chia-Shiung Tsai

Cheng-Ta Wu

Feng-Jia Shiu

Yen-Chang Chu

Biay-Cheng Hseih

Tzu-Hsiang Chen

Ming-Yi Wang

Junbo Chen

Pao-Tung Chen

Cheng Yu Huang

Chih-Kung Chang

Chun-Ming Su

Hsiu-Wen Huang

Jyh-Ming Hung

Ming-Hsien Yang

Yen-Yu Chen

Fu-Lung Hsueh

Kuo-Yu Chou

Chih-Hui Huang

Chia-Huei Lin

Calvin Yi-Ping Chao

Chin-Chia Kuo

Kuo-Chin Huang

Giuseppe Rossi

Honyih Tu

Jung-I Lin

Yuan-Che Lee

Tzeng-Fei Wen

Nien-Tsu Peng

Teng-Yuan Ko

Chia Ching Liao

Chiao-Fu Chang

Ju-Hsin Yen

Chien-Yao Huang

Gary Y Hong

Min-Feng Kao

Tzu-Hsuan Hsu

Ping-Yin Liu

Sheng-Chau Chen

Jiech-Fun Lu

Lan-Lin Chao

Yu-Hung Cheng

Ru-Liang Lee

Xin-Hua Huang

Chuan-Fu Wang

Benjamin Szu-Min Lin

Yueh-Chuan Lee

Chih-Yu Lai

Anchor Chen

Chia-Chan Chen

Jing-Horng Gau

Wei-Li Chen

Tse-Hua Lu

Chun-Tsung Kuo

Tung-I Lin

Wang-Pen Mo

Kai-Chun Hsu

Jung-Chao Chiou

Chung Chien Wang

Yan-Chih Lu

Ping-Fang Hung

Shen-Hui Hong

Tsung-Chien Wu

Lu-Sheng Chou

Hsuan-Han Tseng

The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a masking layer on a first side of a substrate. A first etching process is performed on the first side of the substrate with the masking layer in place. The masking layer is removed. A second wet etching process is performed on the first side of the substrate after removing the masking layer. The first etching process and the second wet etching process collectively form a plurality of topographical features respectively having a triangular shape in a cross-section.

High performance image sensor

A photovoltaic cell includes a germanium-containing well embedded in a single crystalline silicon substrate and extending to a proximal horizontal surface of the single crystalline silicon substrate, wherein germanium-containing well includes germanium at an atomic percentage greater than 50%. A silicon-containing capping structure is located on a top surface of the germanium-containing well and includes silicon at an atomic percentage greater than 42%. The silicon-containing capping structure prevents oxidation of the germanium-containing well. A photovoltaic junction may be formed within, or across, the trench by implanting dopants of a first conductivity type and dopants of a second conductivity type.

Germanium-containing photodetector and methods of forming the same

The present disclosure relates to a CMOS image sensor. The image sensor comprises a pixel region comprising a photodiode disposed within a substrate. A deep trench isolation (DTI) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. A pair of shallow trench isolation (STI) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. A pixel device is disposed at the front-side of the substrate directly overlying the DTI ring. The pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.

Pixel device on deep trench isolation (DTI) structure for image sensor

Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a first semiconductor substrate having a photodetector and a floating diffusion node. A transfer gate is disposed over the first semiconductor substrate, where the transfer gate is at least partially disposed between opposite sides of the photodetector. A second semiconductor substrate is vertically spaced from the first semiconductor substrate, where the second semiconductor substrate comprises a first surface and a second surface opposite the first surface. A readout transistor is disposed on the second semiconductor substrate, where the second surface is disposed between the transfer gate and a gate of the readout transistor. A first conductive contact is electrically coupled to the transfer gate and extending vertically from the transfer gate through both the first surface and the second surface.

Low-noise image sensor having stacked semiconductor substrates

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate having sidewalls that form one or more trenches. The one or more trenches are disposed along opposing sides of a photodiode and vertically extend from an upper surface of the semiconductor substrate to within the semiconductor substrate. A doped region is arranged along the upper surface of the semiconductor substrate and along opposing sides of the photodiode. A first dielectric lines the sidewalls of the semiconductor substrate and the upper surface of the semiconductor substrate. A second dielectric lines sidewalls and an upper surface of the first dielectric. The doped region has a width laterally between a side of the photodiode and a side of the first dielectric. The width of the doped region varies at different heights along the side of the photodiode.

Extra doped region for back-side deep trench isolation

Various embodiments of the present disclosure are directed towards an image sensor with a passivation layer for dark current reduction. A device layer overlies a substrate. Further, a cap layer overlies the device layer. The cap and device layers and the substrate are semiconductor materials, and the device layer has a smaller bandgap than the cap layer and the substrate. For example, the cap layer and the substrate may be silicon, whereas the device layer may be or comprise germanium. A photodetector is in the device and cap layers, and the passivation layer overlies the cap layer. The passivation layer comprises a high k dielectric material and induces formation of a dipole moment along a top surface of the cap layer.

Image sensor with passivation layer for dark current reduction

Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Composite BSI structure and method of manufacturing the same

Germanium-based sensors are disclosed herein. An exemplary germanium-based sensor includes a germanium photodiode and a junction field effect transistor (JFET) formed from a germanium layer disposed on and/or in a silicon substrate. A doped silicon layer, which can be formed by in-situ doping epitaxially grown silicon, is disposed between the germanium layer and the silicon substrate. In embodiments where the germanium layer is on the silicon substrate, the doped silicon layer is disposed between the germanium layer and an oxide layer. The JFET has a doped polysilicon gate, and in some embodiments, a gate diffusion region is disposed in the germanium layer under the doped polysilicon gate. In some embodiments, a pinned photodiode passivation layer is disposed in the germanium layer. In some embodiments, a pair of doped regions in the germanium layer is configured as an e-lens of the germanium-based sensor.

Germanium-based sensor with junction-gate field effect transistor and method of fabricating thereof

The present disclosure relates to a semiconductor device including a semiconductor substrate. A grid structure extends from a first side of the semiconductor substrate to within the semiconductor substrate. An image sensing element is disposed within the semiconductor substrate and is laterally surrounded by the grid structure. A plurality of protrusions are arranged along the first side of the semiconductor substrate. The plurality of protrusions are disposed over the image sensing element and are laterally surrounded by the grid structure. The plurality of protrusions are substantially identical to one another and have a characteristic dimension. An inner surface of the grid structure facing the image sensing element is spaced apart from a point of one of the plurality of protrusions by a predetermined reflective length that is based on the characteristic dimension of the plurality of protrusions.

Semiconductor devices for image sensing

The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a semiconductor substrate. One or more isolation structures are arranged within one or more trenches in the semiconductor substrate. The one or more trenches are disposed along opposing sides of a photo diode region within the semiconductor substrate. The semiconductor substrate includes an undulating exterior having rounded corners arranged laterally between neighboring ones of a plurality of flat surfaces. The rounded corners and the plurality of flat surfaces forming a plurality of triangular shaped protrusions arranged between the one or more isolation structures, as viewed along a cross-sectional view.

In some embodiments, the present disclosure relates to method for forming an image sensor integrated chip. The method includes forming a first photodetector region in a substrate and forming a second photodetector region in the substrate. A floating diffusion node is formed in the substrate between the first photodetector region and the second photodetector region. A pick-up well contact region is formed in the substrate. A first line intersects the floating diffusion node and the pick-up well contact region. One or more transistor gates are formed on the substrate. A second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

Semiconductor imaging device having improved dark current performance

The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

High capacitance MIM device with self aligned spacer

In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.

Vertical gate field effect transistor

Growing community of inventors

Hsin-Chu, Taiwan

Jhy-Jyi Sze