Taiwan Semiconductor Manufacturing Comp. Ltd.

Jhon-Jhy Liaw

Jin-Yuan Lee

Kuo-Hua Pan

Ta-Chun Lin

Chih-Hung Hsieh

Chun-Hung Chen

Yen-Huei Chen

Hung-Jen Liao

Jonathan Tsung-Yung Chang

Cheng-Hung Lee

Chi-Ting Cheng

Dun-Nian Yaung

Ren-Fen Tsui

Dian-Sheg Yu

Kuang-Cheng Tai

Tien-Shao Chuang

Sai-Hooi Yeong

Tzu-Chiang Chen

Hung-Li Chiang

Chao-Ching Cheng

I-Sheng Chen

Chun-Sheng Liang

Chang-Yun Chang

Hsin-Che Chiang

Li-Chih Chao

Shih-Syuan Huang

Chun-Jun Lin

Yu-San Chien

Wesley Lin

Yu-Min Liao

Chao-Cheng Chen

Mong-Song Liang

Cheng-Han Wu

Jyh-Huei Chen

Cheng-Ming Wu

Chia-Wei Chang

Chu-Yun Fu

Yuan-Chang Huang

Yean-Kuen Fang

Kuo Ching Huang

Yi-Miaw Lin

Hsien Wei Chin

Ming-Chang Teng

Ching-Yau Yang

Yu-Ho Chiang

Chia-Shiung Tsai

Li-Chun Tien

Kong-Beng Thei

Shou-Gwo Wuu

Chii-Ming M Wu

Chia-Fu Lee

Hung-Chang Hsieh

Hua-Tai Lin

Hong-Chen Cheng

Subramani Kengeri

Shien-Yang Wu

Yi-Fang Pai

Hsiang-Fan Lee

Yun-Hung Shen

Mu-Chi Chiang

Fang-Shi Jordan Lai

Hou-Ju Li

Chien-Chi Tien

Kuei-Ying Lee

Liang Szuma

Ming-Che Chen

Ding-Shan Wang

Shi-Wei Chang

Shiun-Huan Lai

Jiing-Shin Shyu

Sou-Wein Kuo

Hung-Chi Hsiao

Jacky Lin

Hsien-Ying Tseng

Ging-Fang Yen

A semiconductor device includes a transistor structure disposed on a first side of a substrate and a back-side via structure disposed on a second side of the substrate opposite to the first side. The transistor structure includes a pair of epitaxial structures and a channel feature extending in a channel length direction to be disposed between the epitaxial structures. The channel feature has a width in a channel width direction transverse to the channel length direction. The back-side via structure extends through the substrate so as to be connected to a bottom surface and a sidewall surface of a lower portion of a corresponding one of the epitaxial structures. The back-side via structure has a width in the channel width direction, which is greater than the width of the channel feature.

Semiconductor device with back-side via structure

An integrated circuit structure is provided. The integrated circuit structure includes at least one static random-access memory (SRAM) cell. The SRAM cell includes a first active region, a second active region, a first pull-up transistor, a second pull-up transistor, a first isolation transistor, a second isolation transistor, a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor and a second pull-down transistor. The first active region and the second active region follow a first routing direction. The first pull-up transistor, the second pull-up transistor, the first isolation transistor and the second isolation transistor are formed upon the first active region. The first pass-gate transistor, the second pass-gate transistor the first pull-down transistor and the second pull-down transistor are formed upon the second active region. Each of the at least one SRAM cell has a Y-pitch along the first routing direction. The Y-pitch is 4X contacted poly pitch.

Integrated circuit structure

A memory structure includes a static random access memory (SRAM) cell having a first pass-gate transistor and a second pass-gate transistor, a word-line conductor extending in a first direction, a first source/drain contact, a second source/drain contact, a bit-line conductor in a second direction, and a bit-line-bar conductor extending in the second direction. The second direction is perpendicular to the first direction. The word-line conductor is over and electrically connected to gate electrodes of the first pass-gate transistor and the second pass-gate transistor. The first source/drain contact is under and electrically connected to a source/drain feature of the first pass-gate transistor. The second source/drain contact is under and electrically connected to a source/drain feature of the second pass-gate transistor. The bit-line conductor is under and electrically connected to the first source/drain contact. The bit-line conductor is under and electrically connected to the second source/drain contact.

Memory structure

Semiconductor devices with dual-port memory cells are provided. First inverter includes first pull-up transistor, and first and second pull-down transistors connected in parallel. Second inverter includes second pull-up transistor, and third and fourth pull-down transistors connected in parallel. First and second pass-gate transistors are coupled to the first inverter to form a first port. Third and fourth pass-gate transistors are coupled to the second inverter to form a second port. First and second pass-gate transistors and the first and third pull-down transistors share first continuous active region. The third and fourth pass-gate transistors and the second and fourth pull-down transistors share a second continuous active region. The first and second pull-up transistors and first and second isolation transistors share a third continuous active region. Gates of the first and second isolation transistors are electrically connected to VDD line. Sources of the first and second isolation transistors are floating.

Semiconductor device

A method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.

Semiconductor device and manufacturing method thereof

Memory cells are provided. A memory cell includes a first data storage cell, a second data storage cell and a match cell. The first data storage cell includes a first pull-down transistor, a first pull-up transistor and a first pass-gate transistor. The second data storage cell includes a second pull-down transistor, a second pull-up transistor, and a second pass-gate transistor. The match cell includes a first data transistor and a second data transistor. The first data transistor is electrically connected to the first pull-down transistor, the first pull-up transistor and the first pass-gate transistor. The second data transistor is electrically connected to the second pull-down transistor, the second pull-up transistor and the second pass-gate transistor. The first and second data storage cells and the match cell have the same cell height. The match cell is disposed between the first and second data storage cells.

Memory cell

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

Isolation with multi-step structure

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

A memory structure includes a static random-access memory (SRAM) cell having a cell boundary. The SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor, a first write-port pull-down (PD) transistor, a second write-port PD transistor, a first write-port pass-gate (PG) transistor, a second write-port PG transistor, a first read-port PD transistor, a second read-port PD transistor, a first read-port PG transistor, and a second read-port PG transistor respectively including nanostructures that are vertically stacked from each other. The memory structure further includes a write bit-line conductor and a write bit-line-bar conductor in a first metal layer under the SRAM cell, wherein the write bit-line conductor is electrically connected to a source/drain feature of the first write-port pass-gate transistor and the write bit-line-bar conductor is electrically connected to a source/drain feature of the second write-port pass-gate transistor.

A memory device includes a first static random access memory (SRAM) cell, a second SRAM cell, and a first metal layer. The first SRAM cell includes a first write-port pull-up (PU) transistor and a second write-port PU transistor arranged in a Y-direction, and a first read-port PD transistor and a first read-port PG transistor. The second SRAM cell includes a third write-port PU transistor and a fourth write-port PU transistor arranged in the Y-direction, and a second read-port PD transistor and a second read-port PG transistor. The first and second read-port PD transistors and the first and second read-port PG transistors are arranged in the Y-direction. The first metal layer is over the first SRAM cell and the second SRAM cell. The first metal layer includes a read bit-line conductor extending in the Y-direction and shared by the first SRAM cell and the second SRAM cell.

Memory device

Structures and formation methods of a semiconductor device are provided. The method includes forming a first dummy gate structure across a first fin in a first transistor region of a semiconductor substrate and a second dummy gate structure across a second fin in a second transistor region of the semiconductor substrate. The method also includes selectively introducing atomic or ionic species into the second fin on opposite sides of the second dummy gate structure and etching portions of the first and second fins, so as to form first and second recesses. Each recess is in the respective fin on a side of the respective dummy gate structure. The first recess has a different depth than the second recess. The method further includes forming first and second source/drain features in the first and second recesses, respectively.

Semiconductor device having different source/drain junction depths and fabrication method thereof

Provided is a semiconductor device including a substrate, one hybrid fin, a gate, and a dielectric structure. The substrate includes at least two fins. The hybrid fin is disposed between the at least two fins. The gate covers portions of the at least two fins and the hybrid fin. The dielectric structure lands on the hybrid fin to divide the gate into two segment. The two segments are electrically isolated to each other by the dielectric structure and the hybrid fin. The hybrid fin includes a first portion, disposed between the two segments of the gate; and a second portion, disposed aside the first portion, wherein a top surface of the second portion is lower than a top surface of the first portion.

Semiconductor device and method of forming the same

A semiconductor device includes first and second semiconductor fins, first, second, third and fourth gate structures, and a dielectric structure. The first semiconductor fin and the second semiconductor fin are over a substrate. The first gate structure and the second gate structure respectively extend across the first semiconductor fin and the second semiconductor fin. The first gate structure has a longitudinal axis aligned with a longitudinal axis of the second gate structure. The dielectric structure interposes the first gate structure and the second gate structure. The third gate structure extends across the first and second semiconductor fins. The fourth gate structure extends across the first and second semiconductor fins. The third gate structure is between the fourth gate structure and the dielectric structure. The third gate structure has a maximal width greater than a maximal width of the fourth gate structure.

Semiconductor device with contracted isolation feature

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

Semiconductor device structure and method for forming the same

An IC structure includes first, second, and third circuits. The first circuit includes a first semiconductor fin, a first gate electrode extending across the first semiconductor fin, and a first gate dielectric layer spacing the first gate electrode apart from the first semiconductor fin. The second circuit includes a second semiconductor fin, a second gate electrode extending across the second semiconductor fin, and a second gate dielectric layer spacing the second gate electrode apart from the second semiconductor fin. The third circuit includes a third semiconductor fin, a third gate electrode extending across the third semiconductor fin, and a third gate dielectric layer spacing the third gate electrode apart from the third semiconductor fin. The first gate dielectric layer has a greater thickness than the second gate dielectric layer. The third semiconductor fin has a smaller width than the second semiconductor fin.

Integrated circuit structure including multi-width semiconductor fins

Growing community of inventors

Hsinchu County, Taiwan

Jhon-Jhy Liaw