Texas Instruments Corporation

Jhang W Lee

Mark A Reed

Preferred embodiments disclose include methods of fabrication and integrated circuits (30) in GaAs layers (38, 40) on silicon substrates (32) with the gallium arsenide grown by MBE or MOCVD and containing thermally-strained superlattices (36) and post-growth high temperature annealing to lower defect density. The annealing confines dislocations to a thin network at the interface of the GaAs buffer layer (34) and the silicon substrate (32).

Heteroepitaxy by growth of thermally strained homojunction superlattice

A resonant tunneling diode (30) with anode (40) and cathode (32) separated by binary short-period superlattice tunneling barriers (34,38) with a quantum well (36) between is disclosed. Enhancement and depletion mode diodes are disclosed.

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Richardson, TX, United States of America

Jhang W Lee