Taiwan Semiconductor Manufacturing Comp. Ltd.

Headway Technologies, Incorporated

Jesmin Haq

Zhongjian Teng

Tom Zhong

Yi Yang

Yu-Jen Wang

Dongna Shen

Vinh Lam

Vignesh Sundar

Sahil Patel

Luc Thomas

An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.

STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance

A plurality of conductive via connections are fabricated on a substrate located at positions where MTJ devices are to be fabricated, wherein a width of each of the conductive via connections is smaller than or equivalent to a width of the MTJ devices. The conductive via connections are surrounded with a dielectric layer having a height sufficient to ensure that at the end of a main MTJ etch, an etch front remains in the dielectric layer surrounding the conductive via connections. Thereafter, a MTJ film stack is deposited on the plurality of conductive via connections surrounded by the dielectric layer. The MTJ film stack is etched using an ion beam etch process (IBE), etching through the MTJ film stack and into the dielectric layer surrounding the conductive via connections to form the MTJ devices wherein by etching into the dielectric layer, re-deposition on sidewalls of the MTJ devices is insulating.

Etching and encapsulation scheme for magnetic tunnel junction fabrication

A magnetic tunneling junction (MTJ) structure is described. The MJT structure includes a stress modulating layer on a first electrode layer, where a material of the stress modulating layer is different from a material of the first electrode layer. The MJT structure further includes a MTJ material stack on the stress modulating layer. And the MJT structure further includes a second electrode layer on the MTJ material stack. The stress modulating layer reduces crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

MTJ device performance by adding stress modulation layer to MTJ device structure

A layered thin film device, such as a MTJ (Magnetic Tunnel Junction) device can be customized in shape by sequentially forming its successive layers over a symmetrically curved electrode. By initially shaping the electrode to have a concave or convex surface, the sequentially formed layers conform to that shape and acquire it and are subject to stresses that cause various crystal defects to migrate away from the axis of symmetry, leaving the region immediately surrounding the axis of symmetry relatively defect free. The resulting stack can then be patterned to leave only the region that is relatively defect free.

MTJ device performance by controlling device shape

A three terminal spin-orbit-torque (SOT) device is disclosed wherein a free layer (FL) with a switchable magnetization is formed on a Spin Hall Effect (SHE) layer comprising a Spin Hall Angle (SHA) material. The SHE layer has a first side contacting a first bottom electrode (BE) and an opposite side contacting a second BE where the first and second BE are separated by a dielectric spacer. A first current is applied between the two BE, and the SHE layer generates SOT on the FL thereby switching the FL magnetization to an opposite perpendicular-to-plane direction. The SHE layer is a positive or negative SHA material, and may be a topological insulator such as BiSb. A top electrode is formed on an uppermost hard mask in each SOT device. A single etch through the FL and SHE layer ensures a reliable first current pathway that is separate from a read current pathway.

Integration scheme for three terminal spin-orbit-torque (SOT) switching devices

A MTJ stack is deposited on a bottom electrode. A metal hard mask is deposited on the MTJ stack and a dielectric mask is deposited on the metal hard mask. A photoresist pattern is formed on the dielectric mask, having a critical dimension of more than about 65 nm. The dielectric and metal hard masks are etched wherein the photoresist pattern is removed. The dielectric and metal hard masks are trimmed to reduce their critical dimension to 10-60 nm and to reduce sidewall surface roughness. The dielectric and metal hard masks and the MTJ stack are etched wherein the dielectric mask is removed and a MTJ device is formed having a small critical dimension of 10-60 nm, and having further reduced sidewall surface roughness.

MTJ CD variation by HM trimming

MTJ device performance by adding stress modulation layer to mtj device structure

A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180&#xb0; phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0&#xb0; and 180&#xb0; clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

Critical dimension (CD) uniformity of photoresist island patterns using alternating phase shifting mask

A method for fabricating an improved magnetic tunneling junction (MTJ) structure is described. A bottom electrode is provided on a substrate. A MTJ stack is deposited on the bottom electrode. A top electrode is deposited on the MTJ stack. A first stress modulating layer is deposited between the bottom electrode and the MTJ stack, or a second stress modulating layer is deposited between the MTJ stack and the top electrode, or both a first stress modulating layer is deposited between the bottom electrode and the MTJ stack and a second stress modulating layer is deposited between the MTJ stack and the top electrode. The top electrode and MTJ stack are patterned and etched to form a MTJ device. The stress modulating layers reduce crystal growth defects and interfacial defects during annealing and improve the interface lattice epitaxy. This will improve device performance.

A metal layer and first dielectric hard mask are deposited on a bottom electrode. These are patterned and etched to a first pattern size. The patterned metal layer is trimmed using IBE at an angle of 70-90 degrees wherein the metal layer is reduced to a second pattern size smaller than the first pattern size. A dielectric layer is deposited surrounding the patterned metal layer and polished to expose a top surface of the patterned metal layer to form a via connection to the bottom electrode. A MTJ stack is deposited on the dielectric layer and via connection. The MTJ stack is etched to a pattern size larger than the via size wherein an over etching is performed. Re-deposition material is formed on sidewalls of the dielectric layer underlying the MTJ device and not on sidewalls of a barrier layer of the MTJ device.

Ion beam etching fabricated sub 30nm Vias to reduce conductive material re-deposition for sub 60nm MRAM devices

A process flow for forming magnetic tunnel junction (MTJ) cells with a critical dimension CD&#x2264;60 nm by using a top electrode (TE) hard mask having a thickness&#x2265;100 nm prior to MTJ etching is disclosed. A carbon hard mask (HM), silicon HM, and photoresist are sequentially formed on a MTJ stack of layers. A pattern of openings in the photoresist is transferred through the Si HM with a first reactive ion etch (RIE), and through the carbon HM with a second RIE. After TE material is deposited to fill the openings, a chemical mechanical process is performed to remove all layers above the carbon HM. The carbon HM is stripped and the resulting TE pillars are trimmed to a CD&#x2264;60 nm while maintaining a thickness proximate to 100 nm. Thereafter, an etch process forms MTJ cells while TE thickness is maintained at &#x2265;70 nm.

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Milpitas, CA, United States of America

Jesmin Haq