Aehr Test Systems, Inc.

Probe Technology, Inc.

Jerzy Lobacz

Donald Paul Richmond, Ii

John Dinh Hoang

January Kister

Mark Charles Carbone

Frank Otto Uher

John William Andberg

Krzysztof Dabrowiecki

A burn-in and electrical test system () includes a temperature controlled zone () and a cool zone () separated by a transition zone. The temperature controlled zone () is configured to receive a plurality of wafer cartridges () and connect the cartridges () to test electronics () and power electronics (), which are mounted in the cool zone (). Each of the wafer cartridges () contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics () consists of a pattern generator PCB () and a signal driver and fault analysis PCB () connected together by a parallel bus (). The pattern generator PCB () and the fault analysis PCB () are connected to a rigid signal probe PCB () in cartridge () to provide a straight through signal path. The probe PCB () is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics (). The power distribution system () is connected to a probe power PCB () in the cartridge (). The probe power PCB () has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB (), yet extend a substantial distance away from the probe PCB () at its interconnection ().

Wafer level burn-in and electrical test system and method

A burn-in and electrical test system ( ) includes a temperature controlled zone ( ) and a cool zone ( ) separated by a transition zone The temperature controlled zone ( ) is configured to receive a plurality of wafer cartridges ( ) and connect the cartridges ( ) to test electronics ( ) and power electronics ( ), which are mounted in the cool zone ( ). Each of the wafer cartridges ( ) contains a semiconductor wafer incorporating a plurality of integrated circuits. The test electronics ( ) consists of a pattern generator PCB ( ) and a signal driver and fault analysis PCB ( ) connected together by a parallel bus ( ). The pattern generator PCB ( ) and the fault analysis PCB ( ) are connected to a rigid signal probe PCB ( ) in cartridge ( ) to provide a straight through signal path. The probe PCB ( ) is rigid in order to allow close control of capacitance between each signal line and a backplane, thus providing impedance controlled interconnections between a semiconductor wafer under test and the test electronics ( ). The power distribution system ( ) is connected to a probe power PCB ( ) in the cartridge ( ). The probe power PCB ( ) has at least a bendable portion in order to allow it to be positioned closely adjacent to and parallel with the rigid probe PCB ( ), yet extend a substantial distance away from the probe PCB ( ) at its interconnection ( ).

A cartridge ( ) includes a chuck plate ( ) for receiving a wafer ( ) and a probe plate ( ) for establishing electrical contact with the wafer. In use, a mechanical connecting device ( ) locks the chuck plate and the probe plate fixed relative to one another to maintain alignment of the wafer and the probe plate. Preferably, electrical contact with the wafer is established using a probe card ( ) that is movably mounted to the probe plate by means of a plurality of leaf springs ( ). The mechanical connecting device is preferably a kinematic coupling including a male connector ( ) and first and second opposed jaws ( ). The cartridge can then be removed from the alignment device and placed in a burn-in or test chamber that does not itself require means for aligning the wafer or for providing a probing force.

Wafer level burn-in and test methods

This disclosure proposes an assembly structure for building probe cards to test square integrated circuit chips. The test probe card assembly structure has one or more wings located at 90.degree. angles to each other upon which probes are laid in a parallel manner for attachment to a probe card. This allows construction of the probe card so that probes touch contacts directly. The probe tips do not touch the contacts at an angle .theta., called the fan out angle. The probes also do not differ in their inclination angles .beta.. As a result, the force at which the many probe tips touch the contacts is relatively constant throughout. In addition, the probe tips are less likely to scrub past the surface of the contact onto the insulation surface of the chip and in doing so damage it. The test probe card assembly structure also contains an epoxy groove, which controls epoxy flow so that the position of the probes stays aligned in the correct plane. The epoxy groove also prevents variance in beam length.

Assembly structure for making integrated circuit chip probe cards

A method and device for accurately mounting a probe in a probe card and for maintaining correct location of the probe tip as the probe is used for electronic testing of an IC pad. A membrane having a slot is attached to a support structure of a probe card. The probe tip is inserted into the slot and the probe is affixed to the membrane at the edges of the slot using silicon rubber. The probe is then mounted in the support structure which has a groove for receiving the probe. A distal end of the probe is bonded to the walls of the groove so that the probe is free to move vertically in the groove, but constrained from moving laterally to prevent side-buckling. The membrane and silicon rubber hold the probe tip in proper location during thermal treating of the probe card assembly. Once mounted in the probe card by this method, the probe and probe tip will maintain proper location as they are used for electronic testing of an IC pad. During testing, the probe tip and attached membrane are deflected from their initial position by force of contact with the IC pad. Upon completion of the test, the contact force is removed from the probe tip. The elasticity of the membrane causes the membrane and the attached probe tip to return to their initial position, ensuring that the probe tip is in the proper location for the next test.

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San Mateo, CA, United States of America

Jerzy Lobacz