Dialog Semiconductor (uk) Limited

Jerry Li

Jesus Mennen Belonio, Jr

Ernesto Gutierrez, Iii

Shou Cheng Eric Hu

Melvin Martin

Eric Hu

Francisco Vergara Cadacio

Ian Kent

A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output.

Pillared cavity down MIS-SiP

At least one redistribution layer (RDL) is provided on a silicon die. A passivation layer is deposited on the RDL. First openings having a first diameter are etched in the passivation layer where copper posts are to be formed. A seed layer is deposited over the passivation layer and within the openings. A photoresist layer is coated on the seed layer and patterned to form second openings having a second diameter over the first openings larger than the first diameter. Copper is plated on the seed layer to form copper posts filling the second openings. The silicon die is die attached to a metal substrate. A lamination layer is coated over the silicon die and the copper posts. Third openings are formed through the lamination layer to the copper posts and to metal pads on the metal substrate. Metal vias are formed in the third openings.

Wafer level chip scale package structure

Pillared cavity down MIS-SIP

A method for forming a wafer level chip scale package begins with providing an integrated circuit wafer. Applying a dielectric material to the surface of the integrated circuit wafer. A redistribution conductive layer is formed upon the dielectric material to make contact with the input/output contacts of the integrated circuit. A polymer-based film is applied to the surface of the integrated circuit wafer and is subjected to a compression molding process. Alignment marks are placed on the edge of the integrated circuit wafer. A laser ablation process is implemented to prepare through mold via (TMV) in the cured thermoset plastic material. The solder ball or copper pillar input/output connector is placed in the through mold via (TMV). A reflow process is instigated to connect the input/output connector to the redistribution conductive layer's pad surface.

Integrated circuit package and a method for forming a wafer level chip scale package (WLCSP) with through mold via (TMV)

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Taichung, Taiwan

Jerry Li