Advanced Micro Devices Corporation

Jeremy Sam Lansford

William Jarrett Campbell

Christopher Hans Lansford

H Jim Fulford

Anthony John Toprac

Michael R Conboy

Thomas J Sonderman

Christopher H Raeder

Allen Lewis Evans

W Jarrett Campbell

Bradley J Yellitz

Laura E Faulk

A method for controlling an etch process comprises providing a wafer having at least a first layer and a second layer formed over the first layer. The thickness of the second layer is measured. An etch selectivity parameter is determined based on the measured thickness of the second layer. An operating recipe of an etch tool is modified based on the etch selectivity parameter. A processing line includes an etch tool, a first metrology tool, and a process controller. The etch tool is adapted to etch a plurality of wafers based on an operating recipe, each wafer having at least a first layer and a second layer formed over the first layer. The first metrology tool is adapted to measure a pre-etch thickness of the second layer. The process controller is adapted to determine an etch selectivity parameter based on the measured pre-etch thickness of the second layer and modify the operating recipe of the etch tool based on the etch selectivity parameter.

Method and apparatus for controlling etch selectivity

In one illustrative embodiment, a system is comprised of a semiconductor processing tool, an etcher, a metrology tool, and a controller. The semiconductor processing tool is capable of forming a process layer above a semiconducting substrate. The etcher is capable of removing at least a portion of the process layer. The metrology tool is capable of measuring a first depth of the etch at a first location in a first preselected region of the semiconducting substrate. The controller is capable of comparing the first depth to a desired depth, and varying the temperature of a subsequently processed semiconducting substrate in a region corresponding to the first preselected region in response to the first depth being different from the desired depth.

Method and apparatus for providing etch uniformity using zoned temperature control

Various embodiments of a planarization device and methods of using the same are provided. In one aspect, a device for planarizing a surface of a semiconductor workpiece is provided that includes a table for holding a quantity of an electrically conducting solution thereon. A member is included for holding the semiconductor workpiece such that the surface is in contact with the solution and operates as a working electrode. The member has a first conductor for establishing electrical connection with the semiconductor workpiece. A counter electrode is provided for making electrical connection with the solution and a reference electrode is provided for making electrical connection with the solution with a known electrode potential. A power source is operable to control the electric potential between the working electrode and the counter electrode. Slurry consumption may be dramatically reduced and static etch rate due to aborts may be virtually eliminated.

Chemical mechanical polishing with electrochemical control

Various methods and apparatus for polishing semiconductor workpieces using electrochemically generated species are disclosed. In one aspect, a method of processing is provided that includes contacting a semiconductor workpiece to a solution, electrochemically generating a chemical species in the solution, and polishing the semiconductor workpiece with the aid of the solution.

Electrochemically generated reactants for chemical mechanical planarization

A method is provided, the method comprising planarizing a dielectric layer disposed above a structure layer, exciting surface plasmons in a conductive film disposed in the dielectric layer and detecting photons reflected from the conductive film to determine a change in a surface plasmon resonant angle. The method also comprises determining a thickness of the dielectric layer from the change in the surface plasmon resonant angle.

Surface plasmon resonance-based endpoint detection for chemical mechanical planarization (CMP)

A method for monitoring consumable performance in a processing tool comprises storing a performance model of the processing tool; receiving a consumable item characteristic of a consumable item in the processing tool; determining a predicted processing rate for the processing tool based on the consumable item characteristic and the performance model; determining an actual processing rate of the processing tool; and determining a replacement interval for the consumable item based on at least the actual processing rate. A processing system includes a processing tool and an automatic process controller. The processing tool is adapted to process wafers and includes a consumable item.

Method and apparatus for monitoring consumable performance

A processing line includes a deposition tool, a metrology tool and a controller. The deposition tool is adapted to form a polysilicon layer on a wafer in accordance with a recipe. The metrology tool is adapted to measure a grain size of the polysilicon layer. The controller is adapted to modify the recipe for subsequently formed polysilicon layers based on the measured grain size. A method for controlling a deposition process includes forming a polysilicon layer on a wafer in accordance with a recipe; measuring a grain size of the polysilicon layer; and changing the recipe for subsequently formed polysilicon layers based on the measured grain size.

Method for controlling deposition parameters based on polysilicon grain size feedback

A method includes measuring a surface non-uniformity of a wafer. A current state of an etch processing tool is determined. The surface non-uniformity of the wafer is compared with the current state of the processing tool. An operating parameter of the processing tool is adjusted based on the comparison of the surface non-uniformity of the wafer with the current state of the processing tool. A system includes a processing tool, a plurality of measuring devices, and a process controller. The processing tool is adapted for etch processing of a wafer. The plurality of measuring devices measure a surface non-uniformity of the wafer and determine a current state of the processing tool. The process controller compares the surface non-uniformity of the wafer with the current state of the processing tool and adjusts an operating parameter of the processing tool based on the comparison.

Feed-forward control of an etch processing tool

A method for decreasing variations in gate electrode widths is provided. The method includes providing a wafer having a gate electrode formed thereon and an anti-reflective coating layer formed over at least a portion of the gate electrode. The gate electrode has a width. The width of the gate electrode is measured. A strip rate for a strip tool adapted to remove the anti-reflective coating is determined. The measured width of the gate electrode is compared to a target gate electrode critical dimension to determine an overetch time based on the strip rate. The operating recipe of the strip tool is modified based on the overetch time. A processing line includes a first metrology tool, a strip tool, and a process controller. The first metrology tool is adapted to measure the width of a gate electrode formed on a wafer. The gate electrode has an anti-reflective coating layer formed over at least a portion of the gate electrode. The strip tool is adapted to remove the anti-reflective coating. The process controller is adapted to determine a strip rate for the strip tool, compare the width of the gate electrode to a target gate electrode critical dimension to determine an overetch time based on the strip rate, and modify the operating recipe of the strip tool layer based on the overetch time.

Feedback control of strip time to reduce post strip critical dimension variation in a transistor gate electrode

A method and apparatus for controlling photoresist baking processes. A wafer is provided with the wafer having a layer of photoresist thereon. A first thickness of the photoresist layer is measured, and a first fourier transform infrared (FTIR) spectra of the photoresist layer is generated. Based on the first thickness and first FTIR spectra, a bake time and bake temperature is determined. The wafer is then baked at the bake temperature for the bake time.

Method for controlling photoresist baking processes

In one illustrative embodiment, the method disclosed herein comprises forming a process layer above a semiconducting substrate, forming a layer of photoresist above the process layer, removing the layer of photoresist by performing an etching process, and determining an endpoint of the etching process based upon a temperature of the substrate.

Method of endpointing plasma strip process by measuring wafer temperature

The present invention is directed to the field of semiconductor processing and, more particularly, to a method of planarizing or polishing process layers formed above a surface of a semiconducting substrate. In one illustrative embodiment, the method comprises determining the thickness of a process layer formed above a semiconducting substrate and determining a polishing recipe for said process layer based upon the measured thickness of said process layer.

Method for determining a polishing recipe based upon the measured pre-polish thickness of a process layer

A method includes providing a first wafer having at least one process layer formed thereon. A portion of a first process layer is removed using a polishing process. A portion of at least one of the first process layer and a second process layer is removed using a buffing process for a pre-selected duration of time. A buffed surface of at least one of the first process layer and the second process layer is inspected to determine a post-buff defect density for the inspected process layer. The duration of the buffing process is adjusted for a second wafer based on the determined post-buff defect density of the inspected process layer. A system includes a processing tool, at least one metrology tool, and a process controller. The processing tool is adapted to remove at least a portion of a first process layer of a first wafer using a buffing process for a pre-selected duration of time. The at least one metrology tool is adapted to determine a post-buff defect density of at least one of the first process layer and a second process layer. The process controller is coupled to at least one of the processing tool and the at least one metrology tool. The process controller is adapted to receive the determined post-buff defect density from the at least one metrology tool, and adjust the duration of the buffing process for a second wafer based on the determined post-buff defect density of the first wafer.

Feedback control of polish buff time as a function of scratch count

The present invention is directed to semiconductor processing operations, and, more particularly, to a method and system for adjusting the thickness of process layers based upon the planarization efficiency of polishing operations. In one embodiment, the invention comprises determining the planarization efficiency of polishing operations, and adjusting the manufactured thickness of a process layer based upon the determined planarization efficiency.

Feedback control of deposition thickness based on polish planarization

Various embodiments of an ion implantation apparatus are provided. In one aspect, an apparatus for implanting a workpiece with ions is provided that includes a housing enclosing a first chamber. A source of accelerated ions is provided for directing a beam of ions through the first chamber toward the workpiece. A second chamber is provided for holding the workpiece along with a plurality of longitudinally spaced chambers that are defined by the housing and a plurality of longitudinally spaced bulkheads. Each of the bulkheads has an aperture enabling fluid communication between the plurality of longitudinally spaced chambers and the passage of the beam of ions. A source of gas is coupled to the second chamber. A pumping system is provided for evacuating the first chamber, the second chamber and the plurality of longitudinally spaced chambers. The pumping system and the plurality of longitudinally spaced chambers provide an increase in pressure between the first chamber and the second chamber. The higher pressure level in the second chamber enables the gas to be present in the second chamber in sufficient quantities to impact the workpiece and neutralize charge building thereon. Charge buildup during implantation is reduced.

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Austin, TX, United States of America

Jeremy Sam Lansford