Advanced Micro Devices Corporation

Globalfoundries Inc.

Advance Micro Devices, Inc.

Jeremy Isaac Martin

Paul Raymond Besser

Christian Zistl

Eric M Apelgren

Jonathan B Smith

Minh Van Ngo

Nicholas John Kepler

Srikanteswara Dakshina-Murthy

Hartmut Ruelke

Lie Larry Zhao

Dawn M Hopper

Fred Cheung

Larry Zhao

Richard J Huang

Kashmir S Sahota

Nick Kepler

Ting Yiu Tsui

James J Xie

Srikantewara Dakshina-Murthy

Chii-Chang Lee

Apparatus and methods pertaining to examining electromigration lifespan are disclosed. In one aspect, a method of manufacturing is provided that includes forming a test structure on a semiconductor substrate. The test structure includes a first conductor structure that has a first cross-sectional area and a second conductor structure that has a second cross-sectional area larger than the first cross-sectional area. Current is flowed through the first and second conductor structures at current densities sufficient to cause electromigration in the first and second conductor structures. The current is monitored for drops indicative of electromigration failure of one or both of the first and second conductor structures. The time elapsed before the failure of the one or both of the conductor structures is recorded.

Multiple line width electromigration test structure and method

The present invention is directed to a method of forming semiconductor devices. In one illustrative embodiment, the method comprises defining a photoresist feature having a first size in a layer of photoresist that is formed above a layer of dielectric material. The method further comprises reducing the first size of the photoresist feature to produce a reduced size photoresist feature, forming an opening in the layer of dielectric material under the reduced size photoresist feature, and forming a conductive material in the opening in the layer of dielectric material.

Resist trim process to define small openings in dielectric layers

A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

Dielectric barrier layer for a copper metallization layer having a varying silicon concentration along its thickness

A method and apparatus are provided for a graded PECVD process that continuously modulates a set of flow and pressure conditions while the plasma power is turned on and a film is being deposited. A feedback mechanism specific to a give deposition recipe is used to generate, optimize and maintain a dynamic profile for a first input process parameter that produces a desired dynamic profile for a first output process parameter. An iterative approach produces a gradually converging series of dynamic profiles of an input profile parameter, which eventually succeeds in producing the desired dynamic profile for the first output process parameter of the graded PECVD process.

Method and apparatus for pressure and plasma control during transitions used to create graded interfaces by multi-step PECVD deposition

The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NHdiluted with N, discontinuing the plasma and flow of NHand N, pumping out the chamber; introducing trimethylsilane, NHand He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 &#x212b; to about 800 &#x212b;. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

Copper damascene with low-k capping layer and improved electromigration reliability

A semiconductor component and a method for manufacturing the semiconductor component that mitigates electromigration and stress migration in a metallization system of the semiconductor component. A hardmask is formed over a dielectric layer and an opening is etched through the hardmask and into the dielectric layer. The opening is lined with a barrier layer and filled with an electrically conductive material. The electrically conductive material is planarized, where the planarization process stops on the barrier layer. Following planarization, the electrically conductive material is recessed using either an over-polishing process with highly selective copper slurry or a wet etching process to partially re-open the filled metal-filled trench or via. The recess process is performed such that the exposed portion of the electrically conductive material is below the dielectric layer. A capping layer is then deposited on both the dielectric portion and the exposed metal interconnect portion of the electrically conductive material.

Semiconductor component and method of manufacture

The electromigration resistance of Cu lines is significantly improved by depositing a low-k capping layer thereon, e.g., a silicon carbide capping layer having a dielectric constant of about 4.5 to about 5.5. Embodiments include sequentially treating the exposed planarized surface of inlaid Cu with a plasma containing NH diluted with N , discontinuing the plasma and flow of NH and N , pumping out the chamber; introducing trimethylsilane, NH and He, initiating PECVD to deposit the silicon carbide capping layer, as at a thickness of about 200 &angst; to about 800 &angst;. Embodiments also include Cu dual damascene structures formed in dielectric material having a dielectric constant (k) less than about 3.9.

A Fluorine doped Silicon Oxide (SiO )/Tantalum interface and method for manufacturing the same are provided that ensure the structural integrity of integrated circuits that include a Fluorine doped Silicon Oxide structure and a corresponding Tantalum barrier layer. The Fluorine doped Silicon Oxide (SiO )/Tantalum interface comprises an amount of Silicon Nitride (SiN) in a surface region of a Fluorine doped Silicon Oxide structure. The concentration of Fluorine in the surface region is depleted with respect to a concentration of Fluorine in the remaining portion(s) of the Fluorine doped Silicon Oxide structure. The Fluorine doped Silicon Oxide (SiO )/Tantalum interface also includes an amount of Tantalum Nitride (TaN) in the surface region. Finally, a Tantalum barrier layer is deposited over the surface region.

System and method for adhesion improvement at an interface between fluorine doped silicon oxide and tantalum

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises forming a first opening in the first dielectric layer above at least a portion of the first conductive structure, the first opening having sidewalls, and densifying the sidewalls.

Locally increasing sidewall density by ion implantation

A test circuit includes a wafer, an insulative layer formed on the wafer, and a plurality of test structures formed in the insulative layer. Each of the test structures comprises a first comb having a first plurality of fingers and a second comb having a second plurality of fingers. The first and second pluralities of fingers are interleaved to define a finger spacing between the first and second pluralities of fingers. The finger spacing in a first one of the test structures being different than the finger spacing in a second one of the test structures. A method for characterizing damage in a semiconductor device includes providing a wafer having an insulative layer and a plurality of test structures formed in the insulative layer. The test structures have different geometries. An electrical characteristic of first and second test structures of the plurality of test structures is determined. The electrical characteristics of the first and second test structures is compared. Damage to the insulative layer is characterized based on the comparison.

Method and test structure for characterizing sidewall damage in a semiconductor device

A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.

Sidewall treatment for low dielectric constant (low K) materials by ion implantation

A method is provided, the method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion. The method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N O) and molecular nitrogen (O ).

Graded oxide caps on low dielectric constant (low K) chemical vapor deposition (CVD) films

Degradation of organic low-k interlayer dielectrics during fabrication is substantially prevented or significantly reduced by treatment with a plasma containing a source of hydrogen and N . Embodiments include treating a SiCOH, such as Black Diamond&reg;, ILD with a NH /N plasma after deposition, after forming a damascene opening therein and/or after CMP but prior to capping layer deposition.

NH3/N2-plasma treatment to prevent organic ILD degradation

Damaged low-density silicon oxide-based films having an Si&mdash;O backbone are repaired using a method for driving a self-limiting healing process. According to an example embodiment of the present invention, a deposition precursor and an oxidizer are introduced to a damaged side wall region of a low-density silicon oxide-based film. The unstable damaged portion of the film reacts with the deposition precursor and a thin repair film is grown within the interfacial layer of the damaged film. The repair film provides a strengthened interface, protects the underlying sensitive material from further chemical damage, and can improve the ability to integrate the film.

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Austin, TX, United States of America

Jeremy Isaac Martin