Globalfoundries Inc.

Jeremy Austin Wahl

Nicholas V Licausi

Guillaume Bouche

Andy C Wei

Kingsuk Maitra

Shao Ming Koh

Chanro Park

Gerard M Schmid

Vimal Kumar Kamineni

Richard Farrell

Ryan W Sporer

Nicholas LiCausi

Ajey Poovannummoottil Jacob

Jody Alan Fronheiser

Rohit Pal

Scott Beasor

Hans-Peter Moll

Shariq Siddiqui

Daniel T Pham

Kerem Akarvardar

Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

Interconnect structures with airgaps and dielectric-capped interconnects

The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.

Semiconductor device including a leveling dielectric fill material

A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

Method of manufacturing selective nanostructures into finFET process flow

Methods for forming fins with a straight profile by preventing fin bending during STI fill and annealing are disclosed. Embodiments include providing STI regions separated by Si regions, each topped with a hardmask; planarizing the STI regions; removing the hardmask over a portion of the Si regions, forming recesses; forming a conformal spacer layer over the STI regions and in the recesses; removing horizontal portions of the spacer layer; epitaxially growing Si in each recess, forming fins; and etching the STI regions and a remainder of the spacer layer down to the Si regions to reveal the fins.

Spacer defined fin growth and differential fin width

Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.

Integrated circuits with dual silicide contacts and methods for fabricating same

One disclosed method includes forming a fin in a substrate by etching a plurality of fin-formation trenches, forming a layer of insulating material in the trenches, performing a densification anneal process on the layer of insulating material and, after performing the densification anneal process, performing at least one ion implantation process to form a counter-doped well region in the fin. The method also includes forming an undoped semiconductor material on an exposed upper surface of the fin, recessing the insulating material so as to expose at least a portion of the undoped semiconductor material and forming a gate structure around the exposed portion of the undoped semiconductor material.

Methods of forming FinFET devices with substantially undoped channel regions

A method can include forming a contact trench in a semiconductor structure so that the contact trench extends to a contact formation, the forming including using a hardmask layer, and filling the contact trench with a sacrificial material layer, the sacrificial material layer formed over the contact formation. A semiconductor structure can include a sacrificial material layer over a contact formation.

Method to protect MOL metallization from hardmask strip process

A nanowire device is disclosed that includes first and second nanowires, a gate structure positioned around a portion of the first and second nanowires and a phase change material surrounding at least a portion of the first nanowire in the source/drain regions of the device but not surrounding the second nanowire in the source/drain regions.

Semiconductor device with a multiple nanowire channel structure and methods of variably connecting such nanowires for current density modulation

Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Integrated circuits with dual silicide contacts and methods for fabricating integrated circuits with dual silicide contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having PFET areas and NFET areas. The method selectively forms first silicide contacts from a first metal in the PFET areas. Further, the method selectively forms second silicide contacts from a second metal in the NFET areas. The second metal is different from the first metal.

Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same

One illustrative method disclosed herein includes forming a patterned hard mask layer comprised of a plurality of discrete openings above a structure, wherein the patterned hard mask layer is comprised of a plurality of intersecting line-type features, forming a patterned etch mask above the patterned hard mask layer that exposes at least one, but not all, of the plurality of discrete openings, and performing at least one etching process through the patterned etch mask and the at least one exposed opening in the patterned hard mask layer to define an opening in the structure.

Methods of forming a masking layer for patterning underlying structures

A semiconductor is formed on a (110) silicon (Si) substrate, with improved electron mobility. Embodiments include semiconductor devices having a silicon carbide (SiC) portion in the nFET channel region. An embodiment includes forming an nFET channel region and a pFET channel region in a Si substrate, such as a (110) Si substrate, and forming a silicon carbide (SiC) portion on the nFET channel region. The SiC portion may be formed by ion implantation of C followed by a recrystallization anneal or by epitaxial growth of SiC in a recess formed in the substrate. The use of SiC in the nFET channel region improves electron mobility without introducing topographical differences between NMOS and PMOS transistors.

Strained silicon carbide channel for electron mobility of NMOS

One illustrative method disclosed herein includes the steps of performing a directed self-assembly process to form a DSA masking layer, performing at least one process operation to remove at least one of the features of the DSA masking layer so as to thereby define a patterned DSA masking layer with a DSA masking pattern, performing at least one process operation to form a patterned transfer masking layer having a transfer masking pattern comprised of a plurality of features that define a plurality of openings in the transfer masking layer, wherein the transfer masking pattern is the inverse of the DSA masking pattern, and performing at least one etching process through the patterned transfer masking layer on a layer of material to form a plurality of trench/via features in the layer of material.

Methods of forming trench/via features in an underlying structure using a process that includes a masking layer formed by a directed self-assembly process

One method disclosed herein includes forming a layer of silicon/germanium having a germanium concentration of at least 30% on a semiconducting substrate, forming a plurality of spaced-apart trenches that extend through the layer of silicon/germanium and at least partially into the semiconducting substrate, wherein the trenches define a fin structure for the device comprised of a portion of the substrate and a portion of the layer of silicon/germanium, the portion of the layer of silicon/germanium having a first cross-sectional configuration, forming a layer of insulating material in the trenches and above the fin structure, performing an anneal process on the device so as to cause the first cross-sectional configuration of the layer of silicon/germanium to change to a second cross-sectional configuration that is different from the first cross-sectional configuration, and forming a final gate structure around at least a portion of the layer of silicon/germanium having the second cross-sectional configuration.

Growing community of inventors

Delmar, NY, United States of America

Jeremy Austin Wahl