Adeia Semiconductor Bonding Technologies Inc.

Agilent Technologies, Inc.

Hewlett-packard Company

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies Ecbu IP (singapore) Pte. Ltd.

Avago Technologies Wireless IP (singapore) Pte. Ltd.

Invensas Bonding Technologies, Inc.

Jeremy Alfred Theil

Cyprian Emeka Uzoh

Min Cao

Rajesh Katkar

Guilian Gao

Gary William Ray

Dietrich Werner Vook

Gaius Gillman Fountain, Jr

Laura Wills Mirkarimi

Shawming Ma

Belgacem Haba

Frederick A Perner

Liang Wang

Chandrasekhar Mandalapu

Xin Sun

Richard C Ruby

Daniel Bernardo Roitman

Storrs Townsend Hoen

Mihail Sigalas

Homayoon Haddad

Kevin P Killeen

Ronald Shane Fazzio

Karen L Seaward

Kit M Cham

Wayne M Greene

Charles M C Tan

Gerrit J Kooi

Ron P Varghese

Jane Mei-Jech Lin

Steven A Lupi

Francoise F Mertz

Representative implementations of techniques and methods include chemical mechanical polishing for hybrid bonding. The disclosed methods include depositing and patterning a dielectric layer on a substrate to form openings in the dielectric layer, depositing a barrier layer over the dielectric layer and within a first portion of the openings, and depositing a conductive structure over the barrier layer and within a second portion of the openings not occupied by the barrier layer, at least a portion of the conductive structure in the second portion of the openings coupled or contacting electrical circuitry within the substrate. Additionally, the conductive structure is polished to reveal portions of the barrier layer deposited over the dielectric layer and not in the second portion of the openings. Further, the barrier layer is polished with a selective polish to reveal a bonding surface on or at the dielectric layer.

Direct hybrid bonding of substrates having microelectronic components with different profiles and/or pitches at the bonding interface

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

Method for preparing a surface for direct-bonding

Dies and/or wafers are stacked and bonded in various arrangements including stacks, and may be covered with a molding to facilitate handling, packaging, and the like. In various examples, the molding may cover more or less of a stack, to facilitate connectivity with the devices of the stack, to enhance thermal management, and so forth.

Molded direct bonded and interconnected stack

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

Low temperature bonded structures

Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

Interconnect structures

Chemical mechanical polishing for hybrid bonding

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second conductive interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

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Mountain View, CA, United States of America

Jeremy Alfred Theil