Applied Materials, Inc.

Jeremiah T Pender

Srinivas D Nemani

Qingjun Zhou

Sergey G Belostotskiy

Sean S Kang

Dmitry Lubomirsky

Jungmin Ko

Ying Di Zhang

Tom K Choi

Mang-Mang Ling

Kartik Ramaswamy

Andrew Nguyen

Mehul B Naik

He Ren

Michael D Armacost

Raymond Hoiman Hung

Hongqing Shan

David T Or

Igor V Peidous

Nancy Fung

Sumit Agarwal

Yifeng Zhou

Bradley J Howard

Chia-Ling Kao

Chinh Dinh

Khoi Doan

Henry Fong

Thomas Joseph Kropewnicki

Lina Zhu

Ryan James Patz

Charles Peter Auglis

Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a nitrogen-free plasma process. The method also involves removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.

Method of patterning a low-k dielectric film

Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.

Cyclic spacer etching process with improved profile control

Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber.

Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process

Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.

Methods for barrier layer removal

Methods of patterning silicon nitride dielectric films are described. For example, a method of isotropically etching a dielectric film involves partially modifying exposed regions of a silicon nitride layer with an oxygen-based plasma process to provide a modified portion and an unmodified portion of the silicon nitride layer. The method also involves removing, selective to the unmodified portion, the modified portion of the silicon nitride layer with a second plasma process.

Method of patterning a silicon nitride dielectric film

Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.

Method and system for etching plural layers on a workpiece including a lower layer containing an advanced memory material

Methods of patterning low-k dielectric films are described. In an example, a method of patterning a low-k dielectric film involves forming and patterning a mask layer above a low-k dielectric layer. The low-k dielectric layer is disposed above a substrate. The method also involves modifying exposed portions of the low-k dielectric layer with a plasma process. The method also involves, in the same operation, removing, with a remote plasma process, the modified portions of the low-k dielectric layer selective to the mask layer and unmodified portions of the low-k dielectric layer.

A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates across a varying pattern on a patterned substrate. The method also provides a more rectilinear profile following the etch process. Methods include a sequential exposure of gapfill silicon oxide. The gapfill silicon oxide is exposed to a local plasma treatment prior to a remote-plasma dry etch which may produce salt by-product on the surface. The local plasma treatment has been found to condition the gapfill silicon oxide such that the etch process proceeds at a more even rate within each trench and across multiple trenches. The salt by-product may be removed by raising the temperature in a subsequent sublimation step.

Silicon oxide recess etch

Methods of patterning low-k dielectric films are described.

Method of patterning a low-K dielectric film

Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

Method for fabricating interconnect structures for semiconductor devices

A substrate cleaning method comprises exposing a substrate to an energized process gas to remove residue 60 and resist material from the substrate In one version, the process gas comprises cleaning gas, such as an oxygen-containing gas, and an additive gas, such as NH . In one version, the process gas is introduced to remove residue and resist material from the substrate and to remove residue from surfaces in the process chamber

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San Jose, CA, United States of America

Jeremiah T Pender