Samsung Electronics Co., Ltd.

Jeonghyuk Yim

Kang Ill Seo

Ki-Il Kim

Gil Hwan Son

Byounghak Hong

Kang-ill Seo

Hoonseok Seo

Saehan Park

Daewon Ha

Harsono S Simka

Kang-Ill Seo

Inchan Hwang

Seungchan Yun

Jungsu Kim

Gunho Jo

Rebecca Park

Ming He

Mehdi Saremi

JaeHyun Park

Gilhwan Son

Kiil Kim

Provided is a vertical field-effect transistor (VFET) device which includes: a substrate; a plurality of single-fin VFETs including respective 1fin structures on the substrate; and a plurality of multi-fin VFETs each of which includes a plurality of 2fin structures on the substrate, wherein a fin pitch of the 2fin structures is smaller than a fin pitch of the 1fin structures.

Multi-fin vertical field effect transistor and single-fin vertical field effect transistor on a single integrated circuit chip

Transistor devices are provided. A transistor device includes a substrate. The transistor device includes a lower transistor having a lower gate and a lower channel region on the substrate. The transistor device includes an upper transistor having an upper gate and an upper channel region. The lower transistor is between the upper transistor and the substrate. The transistor device includes an isolation region that separates the lower channel region of the lower transistor from the upper channel region of the upper transistor. Moreover, the lower gate of the lower transistor contacts the upper gate of the upper transistor. Related methods of forming a transistor device are also provided.

Stacked transistors having an isolation region therebetween and a common gate electrode, and related fabrication methods

Integrated circuit devices may include a stacked structure including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper gate electrode, an upper active region in the upper gate electrode, and an upper gate insulator between the upper gate electrode and the upper active region. The upper active region may include an inner layer including a first semiconductor material and an outer layer that extends between the inner layer and the upper gate insulator and includes a second semiconductor material that is different from the first semiconductor material. The lower transistor may include a lower gate electrode, a lower active region in the lower gate electrode, and a lower gate insulator between the lower gate electrode and the lower active region.

Integrated circuit devices including stacked transistors and methods of forming the same

Integrated circuit devices may include two transistor stacks including lower transistors having different threshold voltages and upper transistors having different threshold voltages. Gate insulators of the lower transistors may have different dipole elements or different areal densities of dipole elements, and the upper transistors may have different gate electrode structures.

Integrated circuit devices including transistor stacks having different threshold voltages and methods of forming the same

Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

Devices including stacked nanosheet transistors

Provided is a semiconductor architecture including a carrier substrate, a landing pad included in the carrier substrate, a first semiconductor device provided on a first surface of the carrier substrate, the first semiconductor device including a first component provided on the landing pad, and a second semiconductor device provided on a second surface of the carrier substrate, a second component protruding from the second semiconductor device being provided on the landing pad.

Backside power distribution network semiconductor package and method of manufacturing the same

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Halfmoon, NY, United States of America

Jeonghyuk Yim