Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Hanyang University

Jeong-yun Lee

Yeong-Jong Jeong

Dong-Suk Shin

Si-Hyung Lee

Dong-Hyun Kim

Myeong-Cheol Kim

Seung-hun Lee

Seong-woon Choi

Hyun-jung Lee

Sun-ghil Lee

Bok-Young Lee

Il-Yong Jang

Jung-han Lee

Myung-il Kang

Sun-wook Kim

Jung-Gun You

Kyung-Yub Jeon

Geo-Myung Shin

Bo-ra Lim

Shi Li Quan

Dong-Woo Han

Won-Suk Ahn

Seo-Jin Jeong

Eung-Gwan Kim

Sung-Yong Cho

Kyoung-Sub Shin

Yong-Hoon Kim

Tae-Gon Kim

Kyung-Sun Kim

Geum-jung Seong

Hong Seok Cho

Ken Tokashiki

Jun-ho Yoon

Chin-Wook Chung

Sung-jae Han

Moon-gyu Sung

Sung-Hoon Jang

Ka-soon Yim

Jae-hee Hwang

Seong-Yong Moon

Ah-reum Ji

Moo-Jin Kim

Shi Ii Quan

Edward Nam-kyu Cho

Tae-soon Kwon

An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.

Finfet with various shaped source/drain regions

A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.

Semiconductor device

A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Semiconductor device and method of fabricating the same

Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation

To diagnose plasma in a plasma space, a plurality of floating probes are installed at a plurality of points, respectively, in a plasma space. An electron density ratio at each of the points is calculated by measuring a first probe current of each of the floating probes, the probe current including a DC component. A point ion density and a point electron temperature at each of the points are calculated by measuring a second probe current of each of the floating probes before the electron density ratio is calculated, the second probe current excluding the DC component.

Method and apparatus of diagnosing plasma in plasma space

Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Methods of fabricating FinFET semiconductor devices including dummy structures

Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.

Integrated circuit devices with source/drain regions including multiple segments

A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

FinFET semiconductor devices including dummy structures

A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.

Semiconductor device and method for fabricating the same

A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.

Growing community of inventors

Yongin-si, South Korea

Jeong-yun Lee