Hyundai Electronics Industries Co. Ltd.

Hyundai Electronics Inc. Co., Ltd.

Jeong Mo Hwang

Jeong Hwan Son

Jae Gyung Ahn

Dong Kyun Sohn

Sang Hyun Kim

Jae Sung Roh

Nam Hoon Cho

Sung Kwon Hong

A method for forming a dual gate of a semiconductor device includes the steps of sequentially stacking a gate insulating film, a semiconductor layer, and a low resistance metal layer on a semiconductor substrate having a first well of a first conductivity type and a second well of a second conductivity type, forming first and second gate patterns that include the semiconductor layer and the low resistance metal layer on the substrate corresponding to the first and second wells, forming sidewall spacers at sides of the first and second gate patterns, and exposing the first well and the first gate pattern, implanting impurity ions of the second conductivity type into the exposed first well and the first gate pattern to form a first source and a first drain, exposing the second well and the second gate pattern, implanting impurity ions of the first conductivity type into the exposed second well and the second gate pattern to form a second source and a second drain; and diffusing the impurity ions from the low resistance metal layer into the semiconductor layer to form first and second gate electrodes.

Method for forming dual gate in DRAM embedded with a logic circuit

A semiconductor device and a method for fabricating the same are disclosed, in which floating body effect is reduced by applying a bias to a body in an SOI MOSFET. The semiconductor device includes first and second impurity ion implanting layers of a conductivity type formed in a semiconductor substrate having a buried oxide film and surface silicon layers thereon, first and second transistors of a conductivity type respectively formed on the first and second impurity ion implanting layers, having source/drain regions and a gate, trenches formed between the first and second transistors, single crystal silicon layers connected to any one of the source/drain regions of the respective transistors and the first and second impurity ion implanting layers at sides of the trenches, and carrier exhausting electrodes connected to the first and second impurity ion implanting layers at one sides of the respective transistors, for exhausting carrier generated by ionization impact in the respective transistors.

Semiconductor device and method for fabricating the same

Methods of forming a MOS transistor having dual gates minimizes impurity channeling and diffusion that can occur during impurity injection and activating processes. A method of fabricating the transistor includes the steps of forming a first conduction type well and a second conduction type well in a semiconductor substrate having an isolation region and an active region formed therein. Then, a gate oxide film is formed on an entire surface of the substrate, and a polysilicon layer is deposited on the gate oxide film preferably at a temperature of about 660&deg; C. to about 700&deg; C. and a pressure of about 10 to about 300 Torr. Next, portions of the polysilicon layer and the gate oxide film are selectively removed to form a gate electrode on each of the wells. Impurity ions are injected, having a conduction type opposite a conduction type of the corresponding well, into an exposed surface of each of the wells, to form lightly doped impurity regions. Insulating film sidewalls are formed at sides of each of the gates. Then, first conduction type impurity ions are heavily injected into a surface of the exposed first conduction type well and into the gate electrode formed on the first conduction type well. Also, second conduction type impurity ions are heavily injected into a surface of the exposed second conduction type well and into the gate electrode formed on the second conduction type well. Next, a first heat treatment is conducted in an oxygen ambient and a second heat treatment is conducted in a nitrogen ambient, to diffuse the impurities.

Method for fabricating MOS transistor having dual gate

A method for manufacturing a semiconductor device improves hot carrier characteristic in a device having a thick gate insulating film without being affected by short channel effect, thereby improving reliability of the device. The method for manufacturing a semiconductor device includes the steps of forming gate electrodes having gate insulating films of different thicknesses on a semiconductor substrate, implanting a low-concentration impurity ion into the semiconductor substrate at both sides of the gate electrodes, implanting a nitrogen ion into a portion, where the low-concentration impurity ion is implanted, in the gate insulating film relatively thicker than the other gate insulating film, forming sidewall spacers at both sides of the gate electrodes, and implanting a high-concentration source/drain impurity ion into the semiconductor substrate.

Growing community of inventors

Taejeon-si, South Korea

Jeong Mo Hwang