Samsung Electronics Co., Ltd.

Isc Technology Co., Ltd.

Jeong-Ho Bang

Kyeong-Seon Shin

Ae-Yong Chung

Sung-Ok Kim

Hyun-Seop Shim

Hyoung-Young Lee

Dae-Gab Chi

Ki-Bong Ju

Hyuk Jae Kwon

Eun-Seok Lee

Jae-Il Lee

Young-Gu Shin

Kyoung-Il Heo

Woo-Jin Kim

Byung-Jun Min

Kwang-Kyu Bang

Young-Soo An

Kyeong-seon Shin

Ho-Jeong Choi

Ki-sang Kang

Se-Jang Oh

Jong-Kook Kim

Kun-gu Lee

Soon-Geol Hwang

Hyun-Kyo Seo

Dong-Kyoo Park

Sang-Young Choi

Eun-Sik Kim

Kyoung-Suk Lyu

Woo-Il Kim

Seung-Gyoo Choi

Young-Ki Kwak

Hyun-Geun Iy

Young-Bae Chung

Dae-gab Chi

A test apparatus includes one handler connected to a tester and one test board divided into two or more sites or two or more test boards. Since only the sites on the test board (or test boards) need be duplicated, rather than the loading lanes or sorters of the handler, the test apparatus can be conveniently compact. Further, while testing semiconductor devices on one site or one test board, semiconductor devices in another site or on another test board can be sorted according to the test result. This enables the reduction or elimination of tester idle time to optimize the efficiency of the test apparatus.

Test apparatus having multiple head boards at one handler and its test method

A device and method of manufacturing a fuse region are disclosed. The fuse region may include an interlayer insulating layer formed on a substrate, a plurality of fuses disposed on the interlayer insulating layer, and fuse isolation walls located between the fuses, wherein each of the fuse isolation walls may include lower and upper fuse isolation patterns.

Fuse regions of a semiconductor memory device and methods of fabricating the same

In one embodiment, a connector is made using a mixture of insulating silicone powder and conductive powder. The connector comprises a connector body formed from the insulating silicone powder and on or more preferably regularly arrayed conductive silicone members that are formed by migrating the conductive powder to a site of the connector corresponding to a solder ball of the semiconductor package. The conductive silicone member comprises a high-density conductive silicone part formed to be proximate an upper surface of the connector body and to protrude therefrom and a low-density conductive silicone part formed in substantial vertical alignment beneath the high-density conductive silicone part, the low-density conductive silicone part having a lower surface exposed from a lower surface of the connector body.

Connector for testing a semiconductor package

A test system of a semiconductor device for a handler remote control is provided. The system includes: a tester for testing the semiconductor device; a handler connected to the tester through a GPIB (General Purpose Instruction Bus) communication cable; a tester server connected to the tester to download a test program, handler remote control program and a handler state check program to the tester; and communication data transmitted and received through the GPIB communication cable between the tester and the handler, wherein the communication data has basic communication data for an electrical test of the semiconductor device, communication data for the handler remote control, and communication data for a handler state check.

Test system of semiconductor device having a handler remote control and method of operating the same

Test apparatus having multiple test sites at one handler and its test method

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Multichip package test

A flash memory test system capable of test time reduction and an electrical test method using the same: The invention provides a parallel tester that includes a first memory and a second memory. The first and second memories are used to each supply different data to identical addresses within a plurality of DUTs, thereby making it possible to conduct in parallel tests such as trim tests, repair tests, and invalid block masking test. Thus parallel testing is done to replace testing that was previously done serially.

Flash memory test system and method capable of test time reduction

Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Apparatus and method for performing parallel test on integrated circuit devices

A forced air heat exhaust type of burn-in test apparatus for packages: A first air supply duct provides air to the burn-in chamber and a second air supply duct provides air to supply tubes that direst air into the test sockets that hold the packages. The test sockets have a structure that allows air ventilation of the conductive balls. Accordingly, the apparatus can control the temperature around the packages as well as the temperature in the burn-in chamber, thus preventing conductive ball-melting.

Burn-in test apparatus for BGA packages using forced heat exhaust

An electrical testing method for a semiconductor package for detecting defects of sockets mounted on a device under test (DUT) board is provided. A tester performs electrical test, accumulates electrical test results, and compares the accumulated results to reference values. The result of the comparison decides whether a plurality of sockets mounted on the DUT board can be used or not. The decision results are transmitted to a handler so that the socket having the defects is not used on the DUT board.

Method for electrical testing of semiconductor package that detects socket defects in real time

A method for testing semiconductor devices includes loading a customer tray with semiconductor devices to be tested. Groups of devices are transferred from the customer tray to buffer trays for testing. The number of devices in the customer tray is checked after each transfer. If the customer tray is empty, the number of semiconductor devices in the buffer trays is counted and compared with the number of semiconductor devices that can be tested simultaneously, typically either 64 or 128. If the number of semiconductor devices in the buffer trays is greater than the tester capacity, the semiconductor devices in at least one buffer tray are tested. If the number of semiconductor devices in the buffer trays is smaller than the tester capacity, semiconductor devices that were determined to be low quality in a prior test are loaded into a buffer tray, thus testing both untested and low quality devices together.

Method for testing a remnant batch of semiconductor devices

The present invention relates to a semiconductor device testing system having an advanced testing capability for performing tests on a semiconductor device. A system frame includes both normal and high-speed testing formatters, and a test head is arranged in electrical communication with the system frame. Normal PIN drivers are included to operate the testing system at a first frequency to transmit the signals required to perform tests at a normal speed. High-speed PIN drivers are also included to operate the testing system at a second frequency, higher than the first frequency, to transmit the signals required to perform tests at a higher speed. In this manner, the testing system of this invention is able-to achieve superior testing performance while reducing the overall system production cost.

Semiconductor device testing system

Growing community of inventors

Gyeonggi-do, South Korea

Jeong-Ho Bang