Samsung Electronics Co., Ltd.

Jeong-Dong Choe

Dong-Gun Park

Shin-Ae Lee

Chang-Sub Lee

Seong-Ho Kim

Chang-Woo Oh

Sung-Min Kim

Sung-min Kim

Sung-young Lee

Dong-Won Kim

Hye-Jin Cho

Ki-Hyun Kim

Eun-jung Yun

Dong-Hoon Jang

Young-Bae Yoon

Se-Hoon Lee

Kyoung-hwan Yeo

Choong-Ho Lee

Jae-Man Yoon

Min-sang Kim

Jong Jin Lee

Donghoon Jang

Tae-Yong Kim

Makoto Yoshida

Chul Ho Lee

Hee-Soo Kang

Kyu-Charn Park

Kyoung-Sub Shin

Gyo-young Jin

Ming Li

Hong Seok Cho

Ken Tokashiki

Sang-Yeon Han

Hak-sun Lee

Min-Tai Yu

Woo-Jung Kim

A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

Method of manufacturing a semiconductor device

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

Synchronous pulse plasma etching equipment includes a first electrode and one or more second electrodes configured to generate plasma in a plasma etching chamber. A first radio frequency power output unit is configured to apply a first radio frequency power having a first frequency and a first duty ratio to the first electrode, and to output a control signal including information about a phase of the first radio frequency power. At least one second radio frequency power output unit is configured to apply a second radio frequency power having a second frequency and a second duty ratio to a corresponding second electrode among the second electrodes. The second radio frequency power output unit is configured to control the second radio frequency power to be synchronized with the first radio frequency power or to have a phase difference from the first radio frequency power in response to the control signal.

Synchronous pulse plasma etching equipment and method of fabricating a semiconductor device

Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

Non-volatile memory devices including shared bit lines and methods of fabricating the same

A memory device includes a first floating gate electrode on a substrate between adjacent isolation layers in the substrate, at least a portion of the first floating gate protruding above a portion of the adjacent isolation layers, a second floating gate electrode, electrically connected to the first floating gate electrode, on at least one of the adjacent isolation layers, a dielectric layer over the first and second floating gate electrodes, and a control gate over the dielectric layer and the first and second floating gate electrodes.

Nonvolatile semiconductor device including a floating gate and associated systems

Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer.

Methods of manufacturing charge trap-type non-volatile memory devices

A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.

Semiconductor device including driving transistors

In a non-volatile memory device, active fin structures extending in a first direction may be formed on a substrate. A tunnel insulating layer may be formed on surfaces of the active fin structures and bottom surfaces of trenches that may be defined by the active fin structures. A charge trapping layer and a blocking layer may be sequentially formed on the tunnel insulating layer. A gate electrode structure may include first portions disposed over top surfaces of the active fin structures and second portions vertically spaced apart from portions of the charge trapping layer that may be disposed over the bottom surfaces of the trenches, and may extend in a second direction substantially perpendicular to the first direction. Thus, lateral electron diffusion may be reduced in the charge trapping layer, and thereby the data retention performance and/or reliability of the non-volatile memory device may be improved.

Non-volatile memory device and method of manufacturing the same

Semiconductor device

Nonvolatile semiconductor device including a floating gate, method of manufacturing the same and associated systems

Unit cells of metal oxide semiconductor (MOS) transistors are provided having an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is between the source region and the drain region. A channel region is provided between the source and drain regions. The channel region has a recessed region that is lower than bottom surfaces of the source and drain regions. Related methods of fabricating transistors are also provided.

Metal oxide semiconductor field effect transistors (MOSFETs) including recessed channel regions and methods of fabricating the same

A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

Methods of fabricating semiconductor devices with enlarged recessed gate electrodes

Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate an a MOS transistor on the integrated circuit substrate. The MOS transistor includes a source region, a drain region and a gate. The gate is positioned between the source region and the drain region. A horizontal channel is provided between the source and drain regions. The horizontal channel includes at least two spaced apart horizontal channel regions. Related methods of fabricating MOS transistors are also provided.

Methods of fabricating multichannel metal oxide semiconductor (MOS) transistors

Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

Methods of fabricating field effect transistors having multiple stacked channels

A semiconductor device employs an asymmetrical buried insulating layer, and a method of fabricating the same. The semiconductor device includes a lower semiconductor substrate. An upper silicon pattern is located on the lower semiconductor substrate. The upper silicon pattern includes a channel region, and a source region and a drain region spaced apart from each other by the channel region. A gate electrode is electrically insulated from the upper silicon pattern and intersects over the channel region. A bit line and a cell capacitor are electrically connected to the source region and the drain region, respectively. A buried insulating layer is interposed between the drain region and the lower semiconductor substrate. The buried insulating layer has an extension portion partially interposed between the channel region and the lower semiconductor substrate.

Semiconductor device employing buried insulating layer and method of fabricating the same

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Gyeonggi-do, South Korea

Jeong-Dong Choe