Freescale Semiconductor,inc.

Motorola Corporation

Jennifer H Morrison

Patrice M Parris

Moaniss Zitouni

Richard J De Souza

Xin Lin

Weize Chen

John M McKenna

Edouard De Fr&eacute;sart

Edouard De Frésart

Mark D Griswold

Edouard D deFresart

Anthony Ciancio

Richard J Desouza

Amudha R Irudayam

A tunable antifuse element () includes a substrate material () having an active area () formed in a surface, a gate electrode () having at least a portion positioned above the active area (), and a dielectric layer () disposed between the gate electrode () and the active area (). The dielectric layer () includes a tunable stepped structure (). During operation, a voltage applied between the gate electrode () and the active area () creates a current path through the dielectric layer () and a rupture of the dielectric layer () in a rupture region (). The dielectric layer () is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Tunable antifuse elements

A tunable antifuse element () and method of fabricating the tunable antifuse element, including a substrate material () having an active area () formed in a surface, a gate electrode () having at least a portion positioned above the active area (), and a dielectric layer () disposed between the gate electrode () and the active area (). The dielectric layer () including the fabrication of one of a tunable stepped structure (). During operation, a voltage applied between the gate electrode () and the active area () creates a current path through the dielectric layer () and a rupture of the dielectric layer () in a plurality of rupture regions (). The dielectric layer () is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Tunable antifuse element and method of manufacture

Methods and apparatus are provided for a MOSFET () exhibiting increased source-drain breakdown voltage (BVdss). Source (S) () and drain (D) () are spaced apart by a channel () underlying a gate () and one or more carrier drift spaces (') serially located between the channel () and the source (&#x2032;) or drain (&#x2032;). A buried region (&#x2032;) of the same conductivity type as the drift space (&#x2032;) and the source (&#x2032;) or drain (&#x2032;) is provided below the drift space (&#x2032;), separated therefrom in depth by a narrow gap (&#x2032;) and ohmically coupled to the source (&#x2032;) or drain (&#x2032;). Current flow () through the drift space produces a potential difference (Vt) across this gap (&#x2032;). As the S-D voltage (Vo) and current (, Io) increase, this difference (Vt) induces high field conduction between the drift space (&#x2032;) and the buried region (&#x2032;) and diverts part (, It) of the S-D current (, Io) through the buried region (&#x2032;) and away from the near surface portions of the drift space (&#x2032;) where breakdown generally occurs. Thus, BVdss is increased.

High voltage field effect device and method

By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

Semiconductor device and making thereof

A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

Bipolar junction transistor structure with improved current gain characteristics

A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

Growing community of inventors

Chandler, AZ, United States of America

Jennifer H Morrison