Taiwan Semiconductor Manufacturing Comp. Ltd.

Other

Jenn Ming Huang

Yu-Hua Lee

Min-Hsiung Chiang

Chen-Jong Wang

Cheng-Yeh Shih

James Cheng-Ming Wu

Yi-Miaw Lin

Jin-Yuan Lee

Chung-Cheng Wu

Cheng-Tung Lin

Ming-Ta Lei

Cheng-Ming Wu

Shui-Hung Chen

Tse-Liang Ying

Chue San Yoo

Kuo Ching Huang

Jann-Ming Wu

Chi-Wen Su

Cheng Ming Wu

A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a silicon oxide dielectric layer. There is provided a silicon semiconductor substrate. There is formed upon the silicon semiconductor substrate a blanket silicon oxide pad oxide layer. There is then formed upon the pad oxide layer a patterned silicon nitride masking layer delineating active regions of the silicon semiconductor substrate from isolation regions. There is formed upon the isolation regions by thermal oxidation of the semiconductor silicon substrate in a dry oxidizing environment at an elevated temperature a thick silicon oxide dielectric layer employed as a field oxide (FOX) dielectric isolation layer formed through the silicon nitride patterned masking layer. There is then stripped from the silicon semiconductor substrate the patterned silicon nitride layer, permitting fabrication of microelectronics structures within and upon the semiconductor silicon substrate employing thick silicon oxide field oxide (FOX) dielectric isolation regions without foreign phases or inhomogeneities formed in the &ldquo;bird's beak&rdquo; region therein.

Method for forming high purity silicon oxide field oxide isolation region

A method for making DRAM devices having reduced parasitic capacitance between closely spaced capacitors is achieved. After forming FETs for the memory cells and bit lines having bit-line contacts, a planar insulating layer is formed having an etch-stop layer thereon. Contact openings are etched in the insulating layer and are filled with polysilicon to make contact to capacitor node contact plugs. A relatively thick insulating layer having a low dielectric constant (k) is deposited, and an array of recesses are etched over the node contact plugs for crown-shaped capacitors. A polysilicon layer and an interelectrode dielectric layer are formed in the array of recesses, and another polysilicon layer is patterned to complete the crown capacitors. The low-k insulator between adjacent capacitors reduces the parasitic capacitance and improves data retention of DRAM cells. Alternatively, higher density of memory cells can be formed without increasing parasitic capacitance.

Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device

A planarized surface of a photoresist layer is formed above a layer formed over a hole in a blanket, conformal, silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. A blanket, first photoresist layer was formed above the blanket silicon nitride to fill the damage to the surface caused by the hole. Then the first photoresist layer was stripped leaving a residual portion of the first photoresist layer filling the hole. Next, a blanket, second photoresist layer was formed above the blanket layer. The hole has a neck with a width from about 200 &angst; to about 500 &angst; and the hole has a deep, pocket-like gap with a cross-section with a width from about 500 &angst; to about 1200 &angst; below the narrow neck.

Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule

A method of forming a metal gate integrated with a salicide process on the source and drain regions. A gate dielectric layer and polysilicon/silicon dioxide/silicon nitride dummy gate layers are formed over a substrate structure and patterned to form dummy structures, comprising at least one dummy gate structure. Lightly doped source and drain regions, sidewall spacers, and source and drain regions are formed adjacent to the dummy gate structure. A silicide layer is formed on the source and drain regions by depositing titanium/titanium nitride, performing a rapid thermal anneal, selectively removing unreacted titanium/titanium nitride using NH OH, and performing a second rapid thermal anneal. A blanket dielectric layer is formed over the dummy structures. The blanket dielectric layer, the spacers and the silicon nitride layer of the dummy structures are planarized using a chemical mechanical polishing process. The silicon nitride layer and the silicon dioxide layer of the dummy structures are removed. A titanium nitride layer is formed over the polysilicon layer of the dummy structures, and a tungsten layer is deposited over the titanium nitride layer. The tungsten layer and titanium nitride layer are planarized using a chemical mechanical polishing process, thereby forming polysilicon/titanium nitride/tungsten structures.

Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers

A method for fabricating capacitor-under-bit line (CUB) DRAMs with logic circuits is achieved. CUB are better than capacitor-over-bit line (COB) DRAM circuits because of reduced contact aspect ratios, but CUB require patterning the capacitor top plate over the capacitor rough topography while providing openings to bit line contacts between closely spaced capacitors. A bottom antireflecting coating (BARC) is used in a first method; a non-conform PECVD oxide is used in a second method to make reliable high aspect ratio openings between the capacitors. The BARC is deposited to fill the space between capacitors. A photo-resist layer with improved uniformity is then deposited over the BARC and exposed and developed to form an etch mask with improved resolution for the capacitor top plate. The BARC is plasma etched, and the polysilicon plate is patterned. In the second method a non-conformal PECVD oxide is deposited that is thicker on the top of the capacitors than in the narrow space between capacitors. The PECVD oxide is anisotropically etched back to form self-aligned openings over the bit line contacts, and openings are etched in the polysilicon capacitor top plate aligned over the bit line contact openings. A photoresist etch mask is then used to complete the patterning of the top plate.

Process for making embedded DRAM circuits having capacitor under bit-line (CUB)

A method for making borderless contacts to source/drain areas that overlap the STI is achieved. The method reduces contact shorts between the source/drain and the substrate, and eliminates erosion of the gate oxide to prevent gate/drain shorts. The method involves forming trenches in a silicon substrate, which are filled with a silicon oxide (SiO ) and etched back to form STI surrounding and electrically isolating device areas. The STI is essentially planar with the substrate surface. A gate oxide is formed on the device areas and a polysilicon or polycide layer is patterned to form FET gate electrodes. A first silicon nitride (Si N ) layer is deposited and etched back to form sidewall spacers on the gate electrodes. The STI is recessed using a dip etch. A thin stress-release oxide is formed and a second Si N layer is deposited and etched back to form visors (protective coverings) on the exposed sidewalls of the trench. An interlevel dielectric is deposited and borderless contact openings that extend over the STI can now be etched to the active device areas to provide improved circuit density. When metal plugs are formed in the contact openings, the visor protects the source/drain contacts and the underlying substrate from electrical shorting.

Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions

A method for making an embedded DRAM structure with logic circuits having high performance salicide FETs is achieved. After forming the DRAM FETs and the logic salicide FETs, a planar first insulating layer is deposited, and contact openings are etched and filled with tungsten (W) to form FET and bit-line contacts and to form DRAM capacitor node contacts. A first metal is patterned to form the first metal interconnections including the DRAM bit lines. A second insulating layer is deposited and planarized. Openings are etched to form first vias for the FET metal interconnections and concurrently to form openings for the DRAM capacitor bottom electrodes. The openings are filled with tungsten to form W contacts in the vias and to form bottom electrodes. A thin high-k dielectric is formed over the bottom electrodes, and a second metal is deposited and patterned to form capacitor top electrodes and a second level of metal interconnections. The metal layers and the high-k dielectric layer allow low-temperature processing that is not possible with the more conventional polysilicon DRAM capacitor process. Therefore, this invention prevents salicide FET degradation due to high-temperature processing, while providing a cost-effective process.

Method for making cost-effective embedded DRAM structures compatible with logic circuit processing

This is a method of planarizing a surface of a photoresist layer formed above a layer formed over a gap in a blanket silicon nitride layer which in turn is formed above a keyhole in metallization with SOG layers therebetween on the surface of a semiconductor device. The following steps are performed. Form a blanket, first photoresist layer above the blanket silicon nitride with a damaged surface caused by the gap. Then strip the first photoresist layer leaving a residual portion of the first photoresist layer in the gap. Next, form a blanket, second photoresist layer above the blanket layer. The gap has a neck with a width from about 200 &angst; to about 500 &angst; and the gap has a deep, pocket-like cross-section with a width from about 500 &angst; to about 1,200 &angst; below the narrow neck. Partial stripping of the first photoresist layer, which follows, is performed by an etching process including wet and dry processing.

Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule

A method for fabricating high-aspect-ratio contacts on integrated circuits, such as embedded DRAMs, using a borderless pre-opened hard-mask technique is achieved. After forming gate electrodes for field effect transistors (FETs) and local interconnections from a polycide layer having a silicon nitride (Si,N,) hard mask or cap layer, an anti-reflective coating is used to protect the FET source/drain areas. A photoresist mask and plasma etching are used to remove portions of the hard mask on the interconnections for contact openings, while the anti-reflective protects the source/drain areas. The photoresist mask and the anti-reflective coating are removed, and an interlevel dielectric (ILD) layer is deposited. The high-aspect-ratio contact openings can now be etched in the ILD layer to the source/drain areas, while concurrently etching reliable contact openings to the polycide interconnections where the cap Si,N,has been removed without overetching the source/drain areas.

Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique

The invention teaches a new method that achieves improvements in the creation of shallow Trench Isolation regions. This improvement is achieved by modifying the mask that is used to create the Shallow Trench Isolation regions. The data file that contains the full description of the photoresist image of Shallow Trench Isolation regions, including Optical Corrections, is subdivided into two files. One of the two files contains the descriptions of Shallow Trench Isolation regions that are arranged in array form, the other file contains the descriptions of Shallow Trench Isolation regions that are arranged as single cells. A suitable bias in the form of a small increase or a small decrease is applied to all of the dimensions that are contained within the files. The two files are merged after which conventional processing proceeds.

Geometry design of active region to improve junction breakdown and field isolation in STI process

A method and novel DRAM cell design are described for making DRAM devices with more than a Gigabit memory cells. After forming the FETs and polycide word lines with a cap oxide and sidewall spacers, a thin diffusion protection oxide is deposited and openings are formed for contacts to the substrate. A conductively doped first polysilicon layer is deposited and polished back to the cap oxide. The first polysilicon remaining in the recesses between word lines is patterned to form first plug that are auto self-aligned (zero alignment error) to the word lines to achieve a very high density (Gigabit) memory. A planar first insulating layer with openings for bit lines is formed. Polycide bit lines are formed having a Si3N4 cap layer and sidewall spacers. Contact openings are selectively etched in the first insulating layer to first plugs and self-aligned to the bit lines. A doped second polysilicon layer is deposited and polished back to the Si3N4 cap layer, and the remaining polysilicon between bit lines is patterned to form auto self-aligned capacitor node-contacts to further increase memory cell density. A second insulating layer is deposited, in which DRAM capacitors are formed to complete the high density of memory for Gigabit DRAM devices. The auto self-aligned process eliminates critical photomask alignment and etching.

Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells

A method is provided for making capacitors for future high density circuits. The method increases capacitance while reducing the difficulty in etching the high aspect ratio holes for the capacitor node contacts. After FETs are formed in device areas, a first insulator is deposited and first contact openings are etched for the capacitor node contact. First polysilicon (polySi) plugs are formed in the first contact openings. An etch-stop layer and a second insulating layer are deposited. Second contact openings are aligned over and etched in the second insulating layer to the first polySi plugs. Second polySi plugs are formed in the second contact openings. Openings for capacitors, aligned over and wider than the second polySi plug, are etched in the second insulating layer. The capacitors are completed by forming bottom electrodes with a thin dielectric layer in the capacitor openings and forming a top electrode. This two polysi plug method reduces the need to etch a single high aspect ratio (deep) contacts holes. The second polysi plug also serves as a pillar for increased capacitance. The second contact openings and capacitor openings are etched using a very controllable etch to the etch-stop layer without disturbing the underlying DRAM structure. This allows capacitor design changes for future product generation beyond 0.25 um.

Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar

A method for a self-aligned contact (SAC) that forms top and bottom spacers on the sidewalls of the interlevel dielectric layer. Spaced gate structures are formed between said spaced isolation regions. The gate structure is comprised of a gate oxide layer; a conductive layer; a cap layer. Lightly doped drain regions (LDD) are formed. An interlevel dielectric (ILD) layer is formed. A contact hole is etched that exposes the LDD region between the gate structures and removes a portion of the cap layer. An interlevel dielectric spacer layer is formed over the interlevel dielectric layer, the sidewalls of the contact hole and on the LDD region. In a key step, the interlevel dielectric spacer layer is anisotropically etched forming a top spacer on the sidewalls of the upper opening and a bottom spacer on the lower opening. A contact plug is formed to fill the contact hole and electrically contacting the LDD region. The invention also forms borderless contact hole spacers. The invention's IDL spacers can be thinner than conventional spacers and allow better gap filling for the contact plug.

Self aligned contact using spacers on the ILD layer sidewalls

A method of forming stacked capacitors for a DRAM structure. A thin layer of poly is deposited over the inside surface of the crown holes; the columns of the crown holes form the insulation between the DRAM capacitors. High temperature oxidation is performed on the exposed surface of this layer of poly creating thermal oxide. An anisotropic etch of the surface of the thermal oxide creates a thermal oxide film on the sidewalls of the inter-capacitance insulation. This thermal oxide film is positioned between the capacitors of the DRAM structure. It has superior film quality and as such reduces leakage current between DRAM capacitors. The bottom electrode for the capacitor is formed, ONO is grown on the exposed surface of the bottom electrode (forming the dielectric of the capacitor) after which the top electrode of the capacitor cell is formed.

Cross leakage of capacitors in DRAM or embedded DRAM

A method for forming bit-line and charge-node contact holes that eliminates effects of misalignment when contact etching these holes. A liner is deposited that arrests the etch from burning through the deposited polysilicon and damage the word-line and passgate transistor of a DRAM structure should misalignment occur in the formation of these structures and their surrounding contact plugs. This liner at the same time relaxes restrictions of tolerance for the process of the creation of such holes.

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Hsin-Chu, Taiwan

Jenn Ming Huang