Other

Uniram Technology Inc.

Jeng-Jye Shau

Alexander Shau

David Shau

Albert Yen Shau

Jeng-Ge Shau

Using two or more cameras attached to the eyewear, three-dimensional views with accurate and natural depth perception of the working area can be displayed for users, so that the user can maintain healthy sitting or standing posture while working on patients or objects located below horizontal eye level. Additional functions including eye protection, zoom-in, zoom-out, on-off, lighting control, overlapping, and teleconference capabilities are also supported using electronic, video and audio devices attached to the eyewear. The eyewear can also comprise a face shield designed to protect the user from hazardous droplets, aerosols, harmful wavelengths of light, heat, sparks, flash burn, debris and/or flying objects.

Ergonomic protective eyewear

Using two or more cameras attached to the eyewear, three-dimensional views with accurate and natural depth perception of the working area can be displayed for users, so that the user can maintain healthy sitting or standing posture while working on patients or objects located below horizontal eye level. Additional functions including eye protection, zoom-in, zoom-out, on-off, lighting control, overlapping, and teleconference capabilities are also supported using electronic, video and audio devices attached to the eyewear.

Using two or more cameras attached to the protective eyewear, three-dimensional views with accurate and natural depth perception of the working area can be displayed for users, so that the user can maintain healthy sitting or standing posture while working on patients or objects located below horizontal eye level. Additional functions including eye protection, zoom-in, zoom-out, on-off, lighting control, overlapping, and teleconference capabilities are also supported using electronic, video and audio devices attached to the eyewear.

Hybrid circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a power saving mode. At normal operation mode, a hybrid circuit operates in the same ways as typical CMOS circuits. At power saving mode, the standby leakage current of the circuit is reduced significantly. Typically, most parts of a hybrid circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance. Hybrid circuits can be implemented on integrated circuits comprising multiple-gate MOS transistors.

Low power high performance electrical circuits

Distress signal transmitters of the present invention are designed to maximize the chance for a victim to survive an accident, and minimize the time for a rescue party to find a victim. The preferred embodiments of the distress signal transmitters of the present invention are to be self-powered, self-activated, and to remain fully functional when dropped into salt water. This will allow the Radio Frequency (RF) distress signals to be sent over a long distance, even if the user is unconscious or severely injured. Furthermore, a set of coordinates determined by a Global Positioning System will be transmitted with the S.O.S message in order for search parties to quickly and efficiently pinpoint the location of the victim(s).

Distress signal transmitters

A power saving mode especially useful for memory decoders has been developed. At this power saving mode, the drain-to-source voltage of every MOS transistor in a memory decoder is set to zero, while at normal operation the memory decoder supports the same functions as prior art memory decoders.

Hybrid Super Threshold (SupVt) circuits are CMOS circuits that can function in two different operation modes: a normal operation mode and a SupVt power saving mode. At normal operation mode, a hybrid SupVt circuit operates in the same ways as typical CMOS circuits. At SupVt mode, the standby leakage current of the circuit is reduced significantly, while the circuit still can function at high speed. Typically, most parts of a hybrid SupVt circuit stay in power saving mode. A circuit block is switched into normal operation mode when it needs to operate at full speed. The resulting circuits are capable of supporting ultra-low power operations without sacrificing performance.

Synchronized mechanical switches are configured to support electrical switching circuits operating at frequencies equal to or higher than the frequency of the primary AC power supply. Due to near perfect impedances of mechanical switches as well as accurate timing control mechanisms, the mechanical switching circuits provide timely electrical connections to the terminals of the primary AC power supply to generate proper waveforms suitable to power next stage electrical circuits without the need to use semiconductor devices.

High performance power input circuits using synchronized mechanical switches

The preferred embodiments of the present invention change the switching circuits in switched-mode voltage converter circuits. Instead of switching at full amplitude of input voltage, the preferred embodiments of the present invention provide partial voltage switching signals to the electrical filters. The resulting voltage converter circuits operates at better power efficiency while achieving significantly better space and cost efficiency.

Electrical voltage converter circuits

The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.

High voltage switching circuits

Using printing technologies to fill conductor materials into holes in silicon substrate, the preferred embodiments of the present improve cost efficiency of through-hole connections. Using silicon substrate as cathode terminal during electrical plating that fill holes in a silicon substrate with conductors, the preferred embodiments of the present improve alignment accuracy and cost efficiency of through-hole manufacturing processes.

Area efficient through-hole connections

Using side-wall conductor leads insulated by side-wall insulators to form package level conductor leads for active circuits manufactured on silicon substrate, the preferred embodiments of the present invention significantly reduces the areas of surface mount package chips. Besides area reduction, these methods also provide significant cost saving and reduction in parasitic impedance.

Area reduction for surface mount package chips

Using developed photo-resist materials at the side walls of silicon substrates, the preferred embodiments of the present invention improve alignment accuracy of stacked substrates. Such alignment accuracy improves the area efficiency of side-wall connections as well as through-hole connections. The parasitic impedances of stacked substrate connections are also improved.

Accurate alignment for stacked substrates

Using developed photo-resist materials as insulator materials for through-hole connections, the preferred embodiments of the present invention improve the area efficiency of electrical devices manufactured on silicon substrates. The area efficiency is further improved by opening holes from both sides of silicon substrate to form through-holes. Besides area efficiency, these methods also provide better control in parasitic impedance of through-hole connection.

The present invention provides a solution to avoid the robustness problems of sub-threshold circuits by switching small parts of circuits to nominal-voltage only when they are being used, and switching them back to sub-threshold levels when the operation finishes. Such 'hybrid sub-threshold' approach is capable of supporting ultra-low power operation without the disadvantages of sub-threshold circuits. Hybrid power saving mode for logic circuits provide significant power saving and fast recovery time without performance degradation.

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Palo Alto, CA, United States of America

Jeng-Jye Shau