Industrial Technology Research Institute

Jeng-Hung Sun

Tinghui Huang

Wen-Tung Wang

Jr-Hong Chen

Dou-I Chen

Pi-Fu Chen

Hsixg-Ju Sung

A method for fabricating a thin film transistor that has a multi-layered gate structure of large thickness and the transistors formed are disclosed. In the method, an organic polymeric material layer is spin-coated to planarize a metal gate that has a second metal material deposited in a thin layer on the gate. A suitable metal coating material is molybdenum. A novel planarization process by dry etching is then carried out utilizing a UV spectrum of Mo in an end point detection method to remove all the organic polymeric material from a top planar surface of the metal gate (and the metal coating layer) and then stopping the dry etching process. A dielectric material layer such as silicon nitride is then deposited on top of the metal gate and the remaining organic polymeric material layer to complete the isolation process for the gate. The present invention novel method of utilizing an additional metal coating layer on the metal gate therefore allows an easy identification of the end point in the planarization process wherein an organic polymeric material layer provides a base for depositing a dielectric material thereon for insulating the metal gate. Problems normally associated with the conventional method of insulating a thick metal gate, such as step coverage and void formation problems are thus eliminated in the present invention method.

Multi-layer gate for TFT and method of fabrication

The invention discloses a manufacturing method for improving the reliability of polysilicon thin film transistors to solve electric leaking problem due to the roughness of polysilicon layer surface. In the thin film transistor manufacturing process, a polysilicon layer surface is oxidized to produce a silicon oxide layer which is then removed by an etching solution. This method can planarize bumps on the polysilicon layer generated due to re-crystallization so as to effectively lower the roughness of the polysilicon surface, thus increasing the reliability of thin film transistors.

Manufacturing method for improving reliability of polysilicon thin film transistors

A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n&plus; amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity. The photoresist pattern with incomplete exposure is then etched by an O plasma etching process. The amorphous-silicon layer and the metal layer has the characteristic of an island metal masking structure that protects the active layer from plasma damage in plasma etching process.

Growing community of inventors

Tainan, Taiwan

Jeng-Hung Sun