Taiwan Semiconductor Manufacturing Comp. Ltd.

Haynes and Boone, Llp

Jeng-Horng Chen

Anthony Yen

Shinn-Sheng Yu

Yen-Cheng Lu

Chih-Tsung Shih

Shang-Chieh Chien

Shu-Hao Chang

Chia-Chen Chen

Hung-Chun Wang

Jui-Ching Wu

Ming-Chin Chien

Kuo-Chang Kau

Pei-Shiang Chen

Ru-Gun Liu

Hsin-Chang Lee

Wen-Chun Huang

Chi-Lun Lu

Shih-Chi Wang

Kevin Huang

Chung-Ju Lee

Cheng-Hung Chen

Tzu-Chin Lin

Shy-Jay Lin

Chia-Hao Yu

Chia-Jen Chen

Ta-Cheng Lien

Tsu Shih

Chih-Cheng Lin

Nian-Fuh Cheng

Norman Chen

Shun-Der Wu

Burn Jeng Lin

Chia-Hao Hsu

Tsung-Min Huang

Faruk Krecinic

Chen-Hua Douglas Yu

Shih-Ming Chang

Yun-Yue Lin

Tsung-Yu Chen

Chung-Long Chang

Chieh-Han Wu

Jui-Yu Chang

Tzu-Hsiang Chen

Ching-Wei Shen

Chia-Chi Lin

Tien-Hsi Lee

Amo Chen

Syun-Ming Jang Jang

Hun-Jan Tao

Tsai-Sheng Gau

Hung-Chang Hsieh

Yuan-Hung Chiu

Chia-Ping Chiang

Cheng Kun Tsai

Chieh-Jen Cheng

Tao-Min Huang

Wei-Hung Liu

Hsiang-Yu Chou

Chin-Hsiang Lin

Tien-I Bao

Chien-Hung Lin

Chien-Chih Chen

Pei-Cheng Hsu

Ming-Huan Tsai

Hsin-Chieh Yao

Chia-Hui Lin

Chien-Hsun Chen

Tsiao-Chen Wu

Burn-Jeng Lin

Jen-Yang Chung

Fu-Jye Liang

Chung-Hsing Chang

Shwangming Jeng

Hsien-Kuang Chiu

Tzu-Li Lee

Wei-Chih Lai

Yu-Fu Lin

Bang-Ching Ho

Ying-Yu Chen

Chih-Cheng Chin

Wei-Long Wang

Ming-Jiun Yao

Yi-Ling Hsieh

Fang-Chang Chen

Ying-Chih Lin

Chia-Chun Chung

Amö Chen

Tuane Ying Fang

Shi-Jay Lin

Yun-yue Lin

Pi-Yeh Chia

Chi-Ren Chen

An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.

Mask cleaning

The present disclosure provides an apparatus for a lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame including a material selected from the group consisting of boron nitride (BN), boron carbide (BC), and a combination thereof, a mask, a first adhesive layer that secures the pellicle membrane to the pellicle frame, and a second adhesive layer that secures the pellicle frame to the mask.

Pellicle assembly and method for advanced lithography

A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.

The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Lithography system with an embedded cleaning module

The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a porous pellicle frame, a mask with a patterned surface, a first thermal conductive adhesive layer that secures the pellicle membrane to the porous pellicle frame, and a second thermal conductive adhesive layer that secures the porous pellicle frame to the mask.

A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.

Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.

Method to mitigate defect printability for ID pattern

The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.

Mask with multilayer structure and manufacturing method by using the same

The present disclosure provides an embodiment of a reflective mask that includes a substrate; a reflective multilayer disposed on the substrate; an anti-oxidation barrier layer disposed on the reflective multilayer and the anti-oxidation barrier layer is in amorphous structure with an average interatomic distance less than an oxygen diameter; and an absorber layer disposed on the anti-oxidation barrier layer and patterned according to an integrated circuit layout.

High durability extreme ultraviolet photomask

A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.

Extreme ultraviolet lithography system, device, and method for printing low pattern density features

Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.

System and method for performing lithography process in semiconductor device fabrication

The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.

Pellicle for EUV mask and fabrication thereof

Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.

Material composition and methods thereof

Growing community of inventors

Hsin-Chu, Taiwan

Jeng-Horng Chen