United Microelectronics Corp.

Jeng Gong

Sheng-Hsing Yang

Jiann-Shiun Torng

A multi-layer metallization capacitive structure is provided to a conductive line, such as a power line or signal transmission line in an integrated circuit, where the undesired effect of simultaneous switching noise (SSN) is adverse due to rapid switching of pulses in a digital signal. The multi-layer metallization capacitive structure can help reduce the SSN effect in the integrated circuit by providing at least one metallization layer which extends substantially beneath the conductive line; and at least one dielectric layer sandwiched between the power line and the metallization layer. The multi-layer metallization capacitive structure has an optimal effect if the metallization layer is designed to be precisely equal in width to the power line. The multi-layer metallization capacitive structure has an advantage over the prior art in that it can be formed together with the processing for forming multiple interconnects in the integrated circuit without the need to devise additional processes. Moreover, it requires a reduced layout area to implement as compared to the conventional on-chip capacitor.

Multi-layer metallization capacitive structure for reduction of the simultaneous switching noise in integrated circuits

A high voltage device. A first-type semiconductor substrate having at least a gate formed thereon is provided. The high voltage comprises a second-type first diffusion region in the semiconductor region, a second-type second diffusion region within the first diffusion region, a second-type third diffusion region under the second diffusion region, a field oxide layer on a part of the second diffusion region, and a first-type source/drain region under a surface between the field oxide layer and the gate.

High voltage device

A method of forming high voltage device. A first type semiconductor having at least a gate formed thereon is provided. A first ion implantation with a second type dopant is performed to form a first diffusion region in the semiconductor substrate. An oxide layer is formed on the semiconductor substrate. A second ion implantation with the second type dopant is performed to form a second diffusion region within the first diffusion region. A silicon nitride layer is formed on the oxide layer, through which an opening penetrates to exposed the oxide layer. A third ion implantation with the second type dopant is performed using the silicon nitride layer as a mask to form a third diffusion region within the second diffusion region. Drive-in is performed to deepen the third diffusion region. The silicon nitride layer is removed. The exposed oxide layer is transformed into a field oxide layer. A fourth ion implantation with a first type dopant is performed to form a fourth diffusion region as a source/drain region within the second diffusion region under a surface between the field oxide layer and the gate.

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Hsinchu, Taiwan

Jeng Gong