Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Global Unichip Corporation

Jen-Yang Wen

Min-Hsiu Tsai

Chien-Mo Li

Chih-Mou Tseng

Ming-Tung Chang

In a method for creating a clock domain in a layout of an integrated circuit, a test circuit of the integrated circuit includes a plurality of first scan cells and a plurality of second scan cells, the first scan cells are arranged to be on a first scan chain, and the second scan cells are arranged to be on a second scan chain. The method includes: for a first region in the layout, determining whether the first region needs a test clock domain adjustment according to densities of first scan cells and second scan cells within the first region; and when it is determined that the first region needs the test clock domain adjustment, arranging at least one first scan cell within the first region to be on the second scan chain.

Growing community of inventors

Hualien County, Taiwan

Jen-Yang Wen