Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Chieh Lo

Ru-Gun Liu

Ying-Chou Cheng

Chui-Jung Chiu

Tzu-Chin Lin

Chih-Ming Lai

Shih-Ming Chang

Tsong-Hua Ou

Yu-Po Tang

Ping-Chieh Wu

I-Chang Shih

A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using the measurement tool, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

Method for validating measurement data

A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature, collecting a response signal from the material feature by using a detector in the measurement tool to obtain measurement data, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

A method includes receiving, into a measurement tool, a substrate having a material feature, wherein the material feature is formed on the substrate according to a design feature. The method further includes applying a source signal on the material feature by using a source in the measurement tool having a tool setting parameter, collecting a response signal from the material feature by using a detector in the measurement tool to obtain measurement data, and with a computer connected to the measurement tool, calculating a simulated response signal from the design feature using the tool setting parameter. The method further includes, with the computer, in response to determining that a difference between the collected response signal and the simulated response signal exceeds a predetermined value, causing the measurement tool to re-measure the material feature.

A method is provided for validating measurement data, such as data obtained from a scanning electron microscope using in a semiconductor fabrication facility. The method includes applying a signal on a material feature by using a source in a measurement tool having a tool setting parameter, collecting a response signal from the material feature by using a detector in the measurement tool to obtain the measurement data, calculating a simulated response signal by a smart, and validating the measurement data by comparing the collected response signal with the simulated response signal. The system also includes a design database having a design feature, a measurement tool collecting a response signal, and a smart review engine configured to connect the measurement tool and the design database. The smart engine generates a simulated response signal using the design feature and a measurement tool setting parameter so that the measurement is validated by comparing a collected response signal and a simulated response signal.

A method and computer program are provided for analyzing a set of layers within an integrated circuit design to determine a set of critical points for each layer within the set of layers. The critical points are based at least in part on manufacturer specific process parameters. The method includes assigning a critical point value to each of the critical points within each set of critical points, analyzing a path through the integrated circuit design across multiple integrated circuit design layers, and determining a sum of critical point values of each critical point along the path.

Chip level critical point analysis with manufacturer specific data

A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used.

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Taipei, Taiwan

Jen-Chieh Lo