Samsung Electronics Co., Ltd.

Jei-Hwan Yoo

Jae-Yoon Sim

Jong-hyun Choi

Jae-yoon Sim

Hyun-Soon Jang

Kyu-Nam Lim

Jin-man Han

Bok-Moon Kang

Jae-Yoon Shim

Jong-eon Lee

Hoon Moo Choi

Jong-Won Lee

Sang-Seok Kang

Byung-chul Kim

Kye-Hyun Kyung

Won-Il Bae

Jae-Hoon Joo

Gi-Won Cha

Young-Gu Kang

Jung-hwa Lee

Young-gu Kang

Gi-Woon Cha

A negative voltage generator is controlled responsive to a word line precharge signal. Voltage fluctuations in a negatively biased word line scheme are reduced by using a kicker circuit to provide a predetermined amount of negative charge to shut off a word line during a precharge operation. The negative voltage generator includes first and second negative charge pumps. The second charge pump is activated responsive to the word line precharge signal. A negative voltage regulator can be used to regulate a negative voltage signal. A level shifter uses two voltage dividers and a differential amplifier to reduce response time, output ripple, and sensitivity to process and temperature variations. A negative voltage regulator cancels ripple from a charge pump to provide a stable negative bias voltage and reduce the amount of charge needed to precharge a word line.

Negative voltage generator for a semiconductor memory device

A comparator circuit of a temperature sensor includes an output node and a variable current node. The output node is a first voltage at a given temperature when a current at the variable current node is less than a threshold current, and a different second voltage at the given temperature when the current at the variable current node is more than the threshold current. A variable resistance circuit includes at least n resistors of different resistive values connected in series between the variable current node of the comparator and a supply voltage, where n is an integer of 4 or more. A switching circuit is provided to selectively bypasses individual ones of the n resistors during a test sequence to determine a trip temperature of the sensor.

Temperature sensor and method for detecting trip temperature of a temperature sensor

A semiconductor device package includes a plurality of semiconductor memory devices whose address input terminals are commonly connected to the external address input pins of the package, and an internal address generating device for using an address signal applied through at least one of the address input pins to select one of the memory devices to perform a read/write data operation. Only the selected memory device is enabled to perform the read/write operation on a memory cell corresponding to the received address signal. The external pin configuration of the semiconductor device package is compatible with a conventional memory board layout.

Semiconductor memory device

A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices. Furthermore, the generating circuit generates a bit line sense enable signal with constant delay time that is immune from process changes, voltage fluctuations, and temperature fluctuations.

Semiconductor memory device including a delaying circuit capable of generating a delayed signal with a substantially constant delay time

In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.

Semiconductor memory device and bit line sensing method thereof

A layout structure of a semiconductor memory device having a memory cell array region, a word line drive region proximate the memory cell array, a bit line equalization region spaced apart from the memory cell array region, an impurity region formed between the memory cell array region and the bit line equalization region electrically coupled to the bit line equalization region, and a metal line supplying a bit line equalization voltage to the impurity region, wherein a contact connecting the metal line and the impurity region is formed lateral to the word line drive region rather than between the memory cell array region and the bit line equalization region, so that no contacts are formed directly between the memory cell array region and the bit line equalization region.

Layout structure for dynamic random access memory

A semiconductor device is provided for controlling entry to and exit from a power down (DPD) mode of a semiconductor memory comprising; a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and biasing circuitry for biasing a plurality of nodes of at least one of the plurality of voltage generators to at least one predetermined voltage potential to prevent false triggering of circuits upon entry/exit of DPD mode. Also provided is a semiconductor device, comprising: a plurality of input buffers for buffering a plurality of DPD-type signals for signaling a power down (DPD) condition including a DPD enter/exit signal: an auxiliary buffer for separately buffering the DPD enter/exit signal; a plurality of voltage generators for supplying operating voltages to internal circuit; DPD control circuit for receiving the DPD-type signals to decode DPD enter and exit commands and for outputting a voltage generator control signal to turn off the voltage generators when DPD enter command is decoded, and to turn off the plurality of buffers excluding the auxiliary buffer; and an auto-pulse generator for generating a voltage pulse upon receiving the DPD exit command to initialize internal circuits of the semiconductor device.

Power down voltage control method and apparatus

A memory device utilizing a negatively biased word line scheme diverts word line discharge current from the negative voltage source during a precharge operation, thereby reducing voltage fluctuations and current consumption from the negative voltage source. A main word line, sub-word line, word line enable signal, or other type of word line is coupled to the negative voltage source during a precharge operation. The word line is also coupled to a second power supply during the precharge operation, and then uncoupled from the second power supply after most of the word line discharge current has been diverted. The negative voltage source can then discharge and maintain the word line at a negative bias.

Negatively biased word line scheme for a semiconductor memory device

A semiconductor device for controlling entry to and exit from a power down mode (DPD) of a semiconductor memory, comprising a plurality of voltage generators for providing operating voltages to the semiconductor memory; a DPD controller for detecting a DPD condition and for generating a DPD signal to control the application of the operating voltages to the semiconductor memory; and circuitry for controlling the timing of turning on/off the plurality of voltage generators upon entry/exit of DPD mode to reduce surge current through the semiconductor memory to less than maximum current level.

A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.

Decoding circuit for controlling activation of wordlines in a semiconductor memory device

A voltage detecting circuit includes first and second reference voltage generating circuits. The first reference voltage generating circuit provides a reference voltage during a normal operation mode. The second reference voltage generating circuit provides a reference voltage during a test mode. A comparison voltage generating circuit is also included and provides a comparison voltage during both modes in response to a boosted voltage. A differential amplifier circuit is further included in the voltage detecting circuit. The differential amplifier generates an amplified difference signal that is used to generate a voltage level detection signal. The voltage level detection signal controls a pumping operation for generating the boosted voltage level. A bypass circuit may also be provided to lower a detected boosted voltage level and allow operation at lower voltage levels. The voltage detecting circuit according to this invention is unaffected by process and temperature variations and allows precise and stable voltage detection in either operation mode.

Voltage detecting circuit for semiconductor memory device

A voltage detecting circuit includes a first voltage generator that provides a reference voltage, a second voltage generator that provides a comparison voltage in response to a boosted voltage, and a differential amplifier that provides an amplified difference signal to generate a voltage level detection signal in response to a voltage difference between the reference voltage and the comparison voltage. A bypass circuit is coupled to the amplified signal to detect a target VPP level suitable for a test mode by providing a current path in response to the comparison voltage when the comparison voltage reaches a predetermined level. The voltage detecting circuit thereby allows a precise and stable detecting operation to be performed regardless of the operation mode or process or temperature variations.

Disclosed is a semiconductor memory device having a master fuse circuit, and an address storage and decoding circuit. The address storage and decoding circuit stores address information to assign a defective main cell of main cells, and receives current address information in response to switch control signals. During a burn-in test mode for the main cells, the master fuse circuit generates the switch control signals in response to a bum-in test signal indicating the bum-in test, for shutting the address information off not to be provided to the address storage and decoding circuit, regardless of a connected state of the master fuse.

Growing community of inventors

Kyunggi-do, South Korea

Jei-Hwan Yoo