United Microelectronics Corp.

Jeffrey Wang

Ming-Tsung Liu

D Y Wu

Wen Yang Chen

A buried channel device structure for an electrostatic discharge protection circuit capable of minimizing the effect on the electrostatic discharge protection circuit due to current flowing close to gate oxide layer. A p&plus; ion-doped region is formed above a p-type substrate. The p&plus; ion-doped region serves as a gate terminal. A first and a second n&plus; ion-doped region are also formed in the p-type substrate on each side of the p&plus; gate terminal. In addition, an n-doped region is formed in the p-type substrate under the p&plus; gate terminal between the first and the second n&plus; ion-doped region. A similar buried channel device structure can also be formed on an n-type structure.

Buried channel device structure

A new method of planarizing an integrated circuit is achieved. The dielectric layers between the conductive layers of an integrated circuit are formed and planarized via A first silicon oxide layer is deposited over the metal layer. This is covered with a spin-on-glass layer. This layer is dried by baking. The spin-on-glass layer is now fully cured. The cured spin-on-glass layer is now ion implanted under the conditions of between about 1E15 to 1E17 atoms/cm.sup.2 and energy between about 50 to 100 KeV. A silicon oxide layer is deposited thereover. Via openings are now made through the silicon oxide layers and the spin-on-glass layer and filled with metal. This results in excellent planarity with no poisoned via problems. Most importantly, this method can be used for submicron technologies having conductor lines which are spaced from one another by submicron feature size and can be processed without the use of an etch-back process for the cured spin on and glass layer.

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Hsinchu, Taiwan

Jeffrey Wang