Cadence Design Systems, Inc.

Jeffrey Scott Salowe

Satish Raj

Steven Lee Pucci

Eric Nequist

Roland Ruehl

Karun Sharma

Jeffrey Markham

Min Cao

Yinnie Lee

Olivier Pribetich

Gary Matsunami

Louis K Scheffer

Mark Edward Rossman

Supriya Ananthram

Viral Mankad

Charles T Houck

Some aspects enable users to interactively define a region in an electronic design, identify or generate a track pattern, and assign the track pattern to the region for subsequent physical implementation for the region. Another aspect interactively represents various results on a display apparatus using one or more distinguishing representation schemes. Another aspect is directed at interactive editing a component of an electronic design having track patterns by iteratively modifying a set of track patterns to reach a reduced set of track patterns and by automatically snapping the component to active track(s) in the reduced set for the physical implementation.

Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patterns

Various embodiments implement additional connectivity for electronic designs by identifying one or more regions for a route in normal connectivity of an electronic design, identifying a plurality of seeding segments from the route based at least in part upon the one or more regions, identifying a plurality of additional nodes in the plurality of seeding segments, and generating one or more additional routes connecting the plurality of additional nodes in the plurality of seeding segments. The one or more additional routes are generated without disturbing the normal connectivity including a plurality of Steiner points and the route. Additional nodes differ from Steiner points and are used to implement additional routes that belong to a different route type.

Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designs

One aspect checks and prepares design data () based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation () is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation () may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.

Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniques

One aspect creates or identifies a rule, identifies or creates track pattern(s), and associate the rule with the track pattern(s). The rule is used to guide physical implementation tools to implement electronic designs which not only satisfy the constraints of the rule but also the constraints of the track pattern(s). Some other aspects are directed at interpretation or automatic association or assignment of a layer constraint by determining whether a track pattern on a layer with a first rule matches a second rule, and adding the track pattern to the layer constraint for the second rule on the layer. Another aspect is directed at automatic creation of a rule by creating a new rule, examining each track pattern associated with a first rule, determining whether the new rule matches the first rule, and adding the track pattern to a layer constraint for the new rule.

Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designs

One aspect interconnects two regions subject to different rules and using transition rule(s) in a transition region or cost mechanism(s), where these rules may include soft rule(s), hard rule(s), or combinations thereof. These two regions may reside on the same routing layer or on different routing layers. This aspect allows physical design tools to transition across gridded, gridless, tracked, or trackless regions subject to different rules on the same or different layers. Another aspect interconnects an object subject to the first rule(s) and the second rule(s), while the object satisfies or violates the first rule(s). These aspects use spacetile(s) on a spacetile layer as search probe(s) to find viable implementation solutions, although the spacetile(s) and hence the search probe may violate one or more rules. A spacetile layer may be identified or created for each rule and may be associated with relevant features subject to relevant rule(s).

Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks

Various embodiments implement high current carrying multi-strands of interconnects between two pins in a region of interest within an electronic circuit by performing area-based searches for viable routing solutions using valid intervals. Certain pins that are within a predetermined proximity to each other may be optionally clustered to form a single, wide pin. The region of interest may be first processed to form one or more sets of spacetiles, or the geometries in the region of interest may be projected onto a boundary of the region of interest, to determine the valid interval(s) on along the boundary. The valid intervals may then be used by a router to implement the multi-strands of interconnects. The router also considers the physical, electrical, and manufacturing requirement(s) in implementing the multi-strands of interconnects.

Various aspects described herein create tessellated regions by identifying tessellation lines in one or more directions based at least on fixed shape(s) or route(s). New cells or shapes are added to the design by aligning at least some of the boundary segments of the new cells or shapes with existing tessellation lines. Tessellation lines are dynamically adjustable. At least some tessellated regions are associated with initial or tentative track pattern labels some of which are iteratively updated during implementation of the design. Multiple candidate track patterns may be ranked based on consistency costs to determine a tentative track pattern. Designs may be implemented with a trackless approach in trackless region(s) followed by a tracked approach based at least in part upon the initial or tentative labels that are dynamically adjusted during implementation. Capacities and demands are assessed at boundary segments of cells by using the tracked or trackless approach.

Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designs

Disclosed are methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design in one or more embodiments. One aspect tessellates an area on a layer of an electronic design that is subject to one or more track pattern requirements and dynamically maintains the tessellation structure from the tessellation process for early stages of the design process such as floorplanning, placement, or routing. Another aspect identifies or creates multiple strips or multiple regions for an area on a layer of an electronic design and assigns or associates a track pattern or a track pattern group to each of the multiple strips or multiple regions. In this latter aspect, a track pattern or a track pattern group is no longer required to apply to the entire layer.

Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic design

Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punches for the muting layer, identify an area probe from the spacetiles, and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punches to form spacetiles for the routing layers, determine a via spacetile layer, identify spacetiles as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two muting layers. One of the two routing layers may be a tracked muting layer, and the other may be a trackless routing layer. The tracked muting may be gridded or gridless.

Methods and systems for routing an electronic design using spacetiles

Disclosed are methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks. One aspect identifies an area in an electronic design and a track pattern associated with the area, identifies active tracks in the track pattern, and creates spacetiles with the active tracks. This aspect uses area-based search probes based on spacetiles to find viable implementation solutions to implement the area in the electronic design. Another aspect identifies a tracked area associated with a track pattern and a trackless area and use spacetile(s) and a via spacetile layer to transition between the tracked area and the trackless area for implementation of the electronic design in the tracked or the trackless area of the electronic design.

Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracks

Various aspects described herein identify an area in an electronic design, identify a set of track patterns or track pattern groups for the area based on a set of criteria, and iteratively implement the electronic design in the area using at least some of the set of track patterns. These aspects may dynamically or iteratively update the assignment of one or more track patterns to the region based at least in part upon the implementation of the electronic design in the area or one or more attributes of one or more other areas on the same layer as the current layer of interest or on one or more different layers.

Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic design

Various embodiments identify a routing layer of an electronic design, create spacetile(s) by performing spacetile punch(es) for the routing layer, identify an area probe from the spacetile(s), and routes the electronic design by using the one or more area probes for performing area search for routing solutions. Some embodiments identify two routing layers of an electronic design, perform spacetile punch(es) to form spacetile(s) for the routing layers, determine a via spacetile layer, identify spacetile(s) as one or more area probes based on the via spacetile layer, and routes the electronic design by using the one or more area probes for performing area search for routing solutions while transitioning between the two routing layers. One of the two routing layers may be a tracked routing layer, and the other may be a trackless routing layer. The tracked routing may be gridded or gridless.

Methods, systems, and articles of manufacture for routing an electronic design using spacetiles

Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

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Los Gatos, CA, United States of America

Jeffrey Scott Salowe