Ut-battelle, Inc.

Jeffrey S Vetter

Narasinga Rao Miniskar

Frank Y Liu

Dwaipayan Chakraborty

Mohammad Alaul Haque Monil

Aaron R Young

Pedro Valero Lara

Apparatus and methods are disclosed for scheduling tasks in a heterogeneous computing environment. Coarse scheduling of a received task-set is performed centrally, with tasks dispatched to respective processing resources including one or more accelerators. At each accelerator, sub-tasks of a received task are identified, scheduled, and executed. Data-transfer and computation sub-tasks can be pipelined. The accelerator operates using small tiles of local data, which are transferred to or from a large shared reservoir of main memory. Sub-task scheduling can be customized to each accelerator; coarse task scheduling can work on larger tasks; both can be efficient. Simulations demonstrate large improvements in makespan and/or circuit area. Disclosed technologies are scalable and can be implemented in varying combinations of hard-wired or software modules. These technologies are widely applicable to high-performance computing, image classification, media processing, wireless coding, encryption, and other fields.

Hierarchical task scheduling for accelerators

In a heterogeneous computing environment, a validity flag indicates whether a given memory has a valid copy of a given data object. When the data object is required at a target memory for a scheduled task, another (source) memory having a valid copy of the data object is identified. A protocol guides selection of the source memory based on efficiency of data transfer to the target memory. A data transfer command is generated at runtime, when tasks have been scheduled among respective processors. Execution of the command copies the valid data object from the source memory to the target memory. Superior performance is achieved even in extremely heterogeneous environments. Performance results, variations, and applications are presented.

Efficient memory management for heterogeneous computing

Methods and apparatus for managing circular queues are disclosed. A pointer designates an index position of a particular queue element and contains an additional pointer state, whereby two pointer values (split indexes) can designate the same index position. Front and rear pointers are respectively managed by dequeue and enqueue logic. The front pointer state and rear pointer state distinguish full and empty queue states when both pointers designate the same index position. Asynchronous dequeue and enqueue operations are supported, no lock is required, and no queue entry is wasted. Hardware and software embodiments for numerous applications are disclosed.

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Oak Ridge, TN, United States of America

Jeffrey S Vetter