Raytheon Company

Jeffrey R LaRoche

Thomas E Kazior

Kelly P Ip

John P Bettencourt

Eduardo M Chumbes

Steven D Bernstein

William E Hoke

Boris Solomon Jacobson

Valery S Kaper

Steven Marc Lardizabal

Kamal Tabatabaie

Jason D Adams

Ralph Korenstein

Matthew DeJarld

Lovelace Soirez

Jonathan P Comeau

Susan C Trulli

Paul J Duval

Kamal Tabatabaie Alavi

Michael S Davis

Clay T Long

Ram V Chelakara

A method for fabricating a multi-layer resonator assembly includes sequentially fabricating a plurality of vertically-stacked resonator layers including, for each resonator layer of the plurality of resonator layers, depositing a dielectric layer, forming at least one film bulk acoustic resonator (FBAR) cavity in the deposited dielectric layer, filling each FBAR cavity of the at least one FBAR cavity with a sacrificial material block, and depositing a FBAR material stack over the at least one FBAR cavity. The deposited FBAR material stack is in contact with the sacrificial material block and the dielectric layer. The method further includes removing the sacrificial material block from the at least one FBAR cavity for each resonator layer of the plurality of resonator layers subsequent to sequentially fabricating the plurality of resonator layers.

Multi-layer resonator assembly and method for fabricating same

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

Group III-V semiconductor structures having crystalline regrowth layers and methods for forming such structures

An integrated circuit structure including a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure; an EMF shield enclosing the substrate, the gallium nitride layer and the photoconductive semiconductor switch laterally disposed alongside the transistor on the gallium nitride layer integrated into the integrated circuit structure; and a signal line electronically coupled with the photoconductive semiconductor switch, the signal line penetrating the EMF shield.

On-chip EMF isolation of an integrated circuit coupled with photoconductive semiconductor switch under an on-chip faraday cage

An integrated circuit structure comprising a substrate having an upper surface; a gallium nitride layer disposed on the upper surface of the substrate; and a photoconductive semiconductor switch laterally disposed alongside a transistor on the gallium nitride layer integrated into the integrated circuit structure wherein a regrown gallium nitride material is disposed on the photoconductive semiconductor switch and operatively coupled with the wafer.

Photoconductive semiconductor switch laterally fabricated alongside GaN on Si field effect transistors

A Group III-V semiconductor structure having a semiconductor device. The semiconductor device has a source and drain recess regions extending through a barrier layer and into a channel layer. A regrown, doped Group III-V ohmic contact layer is disposed on and in direct contact with the source and drain recess regions. A gate electrode is disposed in a gap in the regrown, doped Group III-V ohmic contact layer and on the barrier layer A dielectric structure is disposed over the ohmic contact layer and over the barrier layer and extending continuously from a region over the source recess region to one side of the stem to portion and then extending continuously from an opposite side of the stem portion to a region over the drain recess region, a portion of the dielectric structure being in contact with the stem portion and the barrier layer.

A field effect transistor, comprising a gate contact and gate metal forming a vertical structure, such vertical structure having sides and a top surrounded by an air gap formed between a source electrode and a drain electrode of the field effect transistor.

Field effect transistor having improved gate structures

A Field Effect Transistor (FET) structure having: a semiconductor; a first electrode structure; a second electrode structure; and a third electrode structure for controlling a flow of carriers in the semiconductor between the first electrode structure and the second electrode structure; a dielectric structure disposed over the semiconductor and extending horizontally between first electrode structure, the second electrode structure and the third electrode structure; and a fourth electrode passing into the dielectric structure and terminating a predetermined, finite distance above the semiconductor for controlling an electric field in the semiconductor under the fourth electrode structure.

Electrode structure for field effect transistor

A power converter assembly is provided and includes high quality factor (Q) shield-to-transistor integrated low-inductance capacitor elements to divert common mode (CM) currents, high Q shield-to-shield integrated low-inductance capacitor elements to compliment line-to-line filter capacitors and high Q baseplate integrated low-inductance capacitor elements to attenuate residual CM currents.

Heterogeneously integrated power converter assembly

A semiconductor structure having: a Group III-N semiconductor; a first dielectric disposed in direct contact with the Group III-N semiconductor; a second dielectric disposed over the first dielectric, the first dielectric having a higher dielectric constant than the second dielectric; a third dielectric layer disposed on the first dielectric layer, such third dielectric layer having sidewall abutting sides of the second dielectric layer; and a gate electrode contact structure. The gate electrode structure comprises: stem portion passing through, and in contact with, the first dielectric and the second dielectric having bottom in contact with the Group III-V semiconductor; and, an upper, horizontal portion extending beyond the stem portion and abutting sides of the third dielectric layer. An electrical interconnect structure has side portions passing through and in contact with the third dielectric layer and has a bottom portion in contact with the horizontal portion of the gate electrode contact structure.

Nitride structures having low capacitance gate contacts integrated with copper damascene structures

A method for forming a gate structure for a Field Effect Transistor includes providing a semiconductor. A dielectric layer is formed over the semiconductor with an opening therein over a selected portion of the semiconductor. A deposition process is used to selectively deposit a gate metal over the dielectric layer and into the opening, the gate metal being deposited being non-adherent to the dielectric layer by the gate metal deposition process.

Method for forming gate structures for group III-V field effect transistors

A modular high-power converter system includes an electronic power distribution unit configured to output an analog current (AC) voltage to a power bus, and at least one Transmit or Receive Integrated Microwave Module (T/RIMM) that includes a voltage converter unit and a transmitter and receiver (T/R) unit. The voltage converter unit includes at least one analog-to-digital converter (ADC) to convert the AC voltage into a direct current (DC) voltage having a first DC voltage level. The transmitter and receiver (T/R) unit includes a modular-based DC/DC converter to convert the DC voltage into a second DC voltage having a second voltage. The modular-based DC/DC converter includes a modular power converter unit configured to generate the second DC voltage. The modular converter unit is configured to be independently interchangeable with a different modular converter unit.

Flexible power converter architecture based on interposer and modular electronic units

A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Nitride structure having gold-free contact and methods for forming such structures

A method for providing a semiconductor structure includes: providing a structure having: layer comprising silicon, such as a layer of silicon or silicon carbide; a bonding structure; and silicon layer, the bonding structure being disposed between the layer comprising silicon and the silicon layer, the silicon layer being thicker than the layer comprising silicon; and, a Group III-V layer disposed on an upper surface of the layer comprising silicon; forming a Group III-V device in the III-V layer and a strip conductor connected to the device; removing silicon layer and the bonding structure to expose a bottom surface of layer comprising silicon; and forming a ground plane conductor on the exposed bottom surface of the layer comprising silicon to provide, with the strip conductor and the ground plane conductor, a microstrip transmission line.

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Austin, TX, United States of America

Jeffrey R LaRoche