International Business Machines Corporation

Jeffrey P Kasold

Chung H Lam

Paul E Bakeman, Jr

Henry J Geipel, Jr

Robert M Quinn

Andres G Fortino

A non-volatile memory cell uses two different areas for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has dual programming gates disposed on its floating gate. Each programming gate includes a layer of dual electron injector structure (DEIS) and a polysilicon electrode. When writing a '0', one of the programming gates removes charge from the floating gate. When writing a '1', the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.

Gate EEPROM cell

A method of providing less than one micron p-n junction regions for IGFET devices in which a high concentration of arsenic is implanted so that its peak lies near the surface of a semiconductor substrate. Phosphorus is also implanted with an energy to provide a maximum concentration below that of the arsenic and of a magnitude at least one order of magnitude less than that of arsenic. An oxidation/anneal step thermally diffuses the implanted ions to form a junction less than one micron in thickness.

Growing community of inventors

San Jose, CA, United States of America

Jeffrey P Kasold