International Business Machines Corporation

Globalfoundries Inc.

Jeffrey P Bonn

Edmund Juris Sprogis

Robert Mark Rassel

Daniel Nelson Maynard

Daniel Scott Vanslette

Brent A Goplen

Richard Charles Whiteside

Sharon B Sisler

Brian L Kinsman

Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

Integrated circuit and design structure having reduced through silicon via-induced stress

A cost-based algorithm determines semiconductor chip aspect ratios which minimize lithographic processing costs and determines optimum chip matrices for various types of lithographic tools.

Aspect ratio program for optimizing semiconductor chip shape

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Essex Junction, VT, United States of America

Jeffrey P Bonn