Northrop Grumman Systems Corporation

Jeffrey David Hartman

Justin C Hackley

Joel D Strand

Zachary Keane

Aurelius L Graninger

Silai V Krishnaswamy

Wayne Stephen Miller

Micah John Atman Stoutimore

Matthew S Torpey

Benjamin Andrew Copley

Robert Samuel Howell

Deborah P Partlow

Eric Jonathan Stewart

Rowland C Clarke

Bettina A Nechay

Harlan Carl Cramer

Justin Andrew Parke

Thomas J Knight

Edward R Engbrecht

Alfred Paul Turley

Godfrey Augustine

Joseph A Payne

Erica C Elvey

Zachary Kyle Keane

Micah John Stoutimore

Justin A Parke

Harlan C Cramer

A method of forming a multi-chip system is disclosed. The method includes forming one or more bumps on respective conductive contact pads of a first electronic device, forming one or more mini-bumps on respective conductive contact pads of a second electronic device, and aligning respective one or more mini-bumps with respective one or more bumps. The method further includes performing a bump bonding process that exerts compression force on one or both the first electronic device and the second electronic device to compress the one or more mini-bumps into the one or more bumps to form one or more bump bond structures that bond the second electronic device to the first electronic device.

Bump structures for low temperature chip bonding

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

Superconducting bump bond electrical characterization

A flexible connector includes a unitary connector block having first and second board-facing areas. The first and second board-facing areas are longitudinally spaced from each other on a chosen surface of the connector block. The connector block includes a block body transversely separating the chosen surface from an opposing surface oppositely facing from the chosen surface. The connector block includes a flexible connector bridge longitudinally interposed between the first and second board-facing areas. A first connector port is located within the first board-facing area. A second connector port is located within the second board-facing area. A connector trace extends through at least a portion of the block body between the first and second board-facing areas. The connector trace electrically connects the first and second connector ports. Methods of making and using the flexible connector are also included.

Method of providing a flexible connector

A superconducting structure includes a first superconducting device having a plurality of first superconducting contact pads disposed on a top side of a first superconducting device, a second superconducting device having a plurality of second superconducting contact pads disposed on a bottom side of a second superconducting device, and a plurality of superconducting bump structures with a given bump structure coupling respective superconducting contact pads of the plurality of first superconducting contact pads and the second plurality of superconducting pads to one another to bond the first superconducting device to the second superconducting device. Each superconducting bump structure includes a first under bump metallization (UBM) layer disposed on the top surface of a given superconducting contact pad, a second UBM layer disposed on the top surface of a given superconducting contact pads, and a superconducting metal layer coupling the first UBM layer to the second UBM layer.

Method for forming superconducting structures

An apparatus includes a top conductive layer of on an integrated circuit waveguide filter and a bottom conductive layer. The top and bottom conductive layers are coupled via a plurality of couplers that form an outline of the waveguide filter. A dielectric substrate layer is disposed between the top conductive layer and the bottom conductive layer of the integrated circuit waveguide filter. The dielectric substrate layer has a relative permittivity, &#x3b5;r that affects the tuning of the integrated circuit waveguide filter. At least one tunable via includes a tunable material disposed within the dielectric substrate layer and is coupled to a set of electrodes. The set of electrodes enable a voltage to be applied to the tunable material within the tunable via to change the relative permittivity of the dielectric substrate layer and to enable tuning the frequency characteristics of the integrated circuit waveguide filter.

Voltage controlled tunable filter

An angled circuit board connector includes a unitary connector block having first and second board-contacting faces. The first and second board-contacting faces are arranged relative to each other at an operative angle. The connector block includes a block body. The first and second board-contacting faces face outward from the block body. A first connector port is located on the first board-contacting face. A second connector port is located on the second board-contacting face. A connector trace extends through at least a portion of the block body between the first and second board-contacting faces. The connector trace electrically connects the first and second connector ports.

Angled circuit board connector

The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

Superlattice crenelated gate field effect transistor

Embodiments of a method and apparatus for removing metallic nanotubes without transferring CNTs from one substrate to another substrate provide two methods of transferring a thin layer of crystalline ST-cut quartz wafer to the surface of a carrier silicon wafer for subsequent CNT growth, without resorting to CNT transfer. In other words, embodiments of a method and apparatus allow CNTs to be grown on the same substrate that metallic nanotube removal is performed, therefore eliminating the costly and messy step of transferring CNTs from one substrate to another. This is achieved through a residual thin layer of crystalline ST-cut quartz layer on a silicon wafer. The ST-cut quartz wafer promotes aligned growth of CNTs, while the underlying silicon wafer allows backgate burnout.

Method and apparatus for removing metallic nanotubes without transferring carbon nanotubes from one substrate to another substrate

High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates

First and second semiconductor wafers are bonded together, with at least one of the wafers having a first layer of silicon, an intermediate oxide layer and a second layer of silicon. The first silicon layer is initially mechanically reduced by around 80% to 90% of its thickness. The remaining silicon layer is further reduced by a plasma etch which may leave an uneven thickness. With appropriate masking the uneven thickness is made even by a second plasma etch. Remaining silicon is removed by a dry etch with XeF2 or BrF3 to expose the intermediate oxide layer. Prior to bonding, the semiconductor wafers may be provided with various semiconductor devices to which electrical connections are made through conducting vias formed through the exposed intermediate oxide layer.

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Severn, MD, United States of America

Jeffrey David Hartman