Intel Corporation

Jeffrey D Gilbert

Krishnakanth Venkata Sistla

Yen-Cheng Liu

Kai Cheng

Ganapati Srinivasa

Zhong-Ning George Cai

Vivek Garg

Dean A Mulla

Mark Rowland

George Cai

Suresh Doraiswamy

Harris D Joyce

Christopher P Mozak

Tsvika Kurts

Julius Yuli Mandelblat

Durgesh Srivastava

Bryan L Spry

Liqun Cheng

William G Auld

Balaji P Ramamoorthy

Preventing request conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to manage request conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches shared amongst a set of cores or processors or agents.

Resolving multi-core shared cache access conflicts

In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.

Dynamically adjusting power of non-core processor circuitry including buffer circuitry

A method and apparatus for cache coherency sequencing implementation and an adaptive LLC access priority control is disclosed. One embodiment provides mechanisms to resolve last level cache access priority among multiple internal CMP cores, internal snoops and external snoops. Another embodiment provides mechanisms for implementing cache coherency in multi-core CMP system.

Cache coherency sequencing implementation and adaptive LLC access priority control for CMP

In one embodiment, the present invention includes a method for receiving an indication of a pending capacity eviction from a caching agent, determining whether an invalidating writeback transaction from the caching agent is likely for a cache line associated with the pending capacity eviction, and if so moving a snoop filter entry associated with the cache line from a snoop filter to a staging area. Other embodiments are described and claimed.

Reducing back invalidation transactions from a snoop filter

A system and method for signaling a deferred response to a data request in a bus connected system is described. In one embodiment, a responding agent on the bus issues a deferred response message when it cannot supply the requested data in a short period of time. When the responding agent knows that the requested data will shortly arrive in its buffers, it may first send an identification signal to the requesting agent, indicating to the requesting agent that it should prepare to receive the data shortly. After one or more bus clock cycles, the responding agent may then subsequently send the corresponding data message to the requesting agent.

System and method to reduce memory latency in microprocessor systems connected with a bus

In various embodiments, hardware, software and firmware or combinations thereof may be used to prevent cache conflicts within microprocessors and/or computer systems. More particularly, embodiments of the invention relate to a technique to prevent cache conflicts within a processor and/or computer system in which a number of accesses may be made to a particular cache or group of caches.

Preventing system snoop and cross-snoop conflicts

In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

Common analog interface for multiple processor cores

A snoop filter maintains data coherency information for multiple caches in a multi-processor system. The Exclusive Ownership Snoop Filter only stores entries that are exclusively owned by a processor. A coherency engine updates the entries in the snoop filter such that an entry is removed from the snoop filter if the entry exits the exclusive state. To ensure data coherency, the coherency engine implements a sequencing rule that decouples a read request from a write request.

Exclusive ownership snoop filter

Methods and apparatus to perform direct cache access in multiple core processors are described. In an embodiment, data corresponding to a direct cache access request is stored in a storage unit and a corresponding read request is generated. Other embodiments are also described.

Direct cache access in multiple core processors

A method and apparatus for cache coherency states is disclosed. In one embodiment, a cache accessible across two interfaces, an inner interface and an outer interface, may have a joint cache coherency state. The joint cache coherency state may have a first state for the inner interface and a second state for the outer interface, where the second state has higher privilege than the first state. In one embodiment this may promote speculative invalidation. In other embodiments this may reduce snoop transactions on the inner interface.

Method and apparatus for joint cache coherency states in multi-interface caches

A method and apparatus for adaptive multiple line prefetching. In one embodiment, the method includes the identification of a prefetch depth. As described herein, a prefetch depth may refer to a number of memory lines to be prefetched to temporary (cache) memory. Once the prefetch depth is identified, prefetching is performed according to the identified prefetch depth. During the prefetching, the prefetching is adjusted as changes in the prefetch depth are detected. Accordingly, the dynamic adaptive multi-line prefetching mechanism described herein promotes higher system performance by the use of a more efficient prefetching mechanism.

Apparatus and method for an adaptive multiple line prefetcher

A method and apparatus for improved performance for handling priority agent bus requests when symmetric agent bus parking is enabled is disclosed. In one embodiment, a modified priority agent may be used. The modified priority agent may assert an unused symmetric agent bus request when it asserts its priority agent bus request. When a symmetric agent parks on the bus, continually asserting its symmetric agent bus request, the assertion of the otherwise unused symmetric agent bus request may cause the symmetric agent to withdraw its symmetric agent bus request. This may reduce bus response time for subsequent modified priority agent bus requests.

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Hillsboro, OR, United States of America

Jeffrey D Gilbert