Intel Corporation

California Micro Devices Corp.

Jeffrey C Kalb, Jr

Dominick L Richiuso

Jeffrey C Kalb

John C Jorgensen

Robert W Daywitt

An active termination circuit for terminating a transmission line in bused or networked device, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor. The first threshold reference device being configured to maintain a base of the first clamping transistor at about V,lower than the second reference voltage level. There is further included a second threshold reference device coupled to the second clamping transistor, the second threshold reference device being configured to maintain a base of the second clamping transistor at about V,higher than the first reference voltage level.

Termination circuits and methods for bused and networked devices

A method for detecting defects in a semiconductor device using IDDQ testing techniques that is not dependent upon the background leakage current for defect determination. One embodiment of the present invention measures a first quiescent current at a first voltage, measures a second quiescent current at a second voltage; determines a defect current component from the two measurements and evaluates the defective current against a screening value.

Background leakage zeroing by temperature and voltage dependence for IDDQ measurement and defect resolution

A method for detecting defects in a CMOS integrated circuit. In one embodiment, an integrated circuit is exercised to a first cycle. IDDQ testing is then performed on the integrated circuit. Next, the integrated circuit is irradiated with for example ultraviolet radiation, which in one embodiment sets floating gates to an intermediate operating value. Next, IDDQ testing is performed again and any differences in IDDQ between the two IDDQ test measurements may be attributed to floating gate defects in the integrated circuit.

UV methods for screening open circuit defects in CMOS integrated circuits

An active termination circuit for terminating a transmission line in memory bus, which might include a plurality of devices. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor. The first threshold reference device being configured to maintain a base of the first clamping transistor at about V.sub.BE lower than the second reference voltage level. There is further included a second threshold reference device coupled to the second clamping transistor, the second threshold reference device being configured to maintain a base of the second clamping transistor at about V.sub.BE higher than the first reference voltage level.

Termination circuits and methods for memory buses and devices

An active termination circuit for terminating a transmission line in an electronic device. The active termination circuit is configured to clamp a voltage level on the transmission line to one of a first reference voltage level and a second reference voltage level. The active termination circuit includes a first clamping transistor coupled to a transmission line terminal and a first terminal. The transmission line terminal is configured to be coupled to the transmission line in the electronic device. The first terminal is configured to be coupled to the first reference voltage level in the electronic device. There is included a second clamping transistor coupled to the transmission line terminal and a second terminal. The second terminal is configured to be coupled to the second reference voltage level in the electronic device. There is also included a first threshold reference device coupled to the first clamping transistor. The first threshold reference device being configured to maintain a base of the first clamping transistor at about V.sub.BE lower than the second reference voltage level. There is further included a second threshold reference device coupled to the second clamping transistor, the second threshold reference device being configured to maintain a base of the second clamping transistor at about V.sub.BE higher than the first reference voltage level.

Termination circuits and methods therefor

A method for detecting defects in a CMOS integrated circuit. In one embodiment, all pins on an integrated circuit chip are initially grounded. Next, the chip is exposed to ultraviolet light which will discharge the voltage on a floating gate in the integrated circuit to zero volts. Next, the chip is powered up to a normal operating condition voltage levels. That is, normal operating voltages are applied to V.sub.CC while V.sub.SS pins remain grounded. As a result, the floating gates in the integrated circuit will stabilize at an intermediate logic value determined by the voltage divider relationship determined by the parasitic capacitances between the floating gates, V.sub.CC and V.sub.SS. Next, IDDQ testing is performed on the chip. Since the floating gates have been set to an intermediate logical value, any floating gate defects will be detected with IDDQ testing since a substantially high quiescent current will result with the floating gate node voltages set to an intermediate value. Thus, in accordance with the teachings of the present invention, devices suffering from open circuit floating gate may be identified.

A method for detecting defect in a semiconductor device using IDDQ testing techniques that are not dependent upon the background leakage current for defect resolution. One embodiment of the present invention uses device sampling, i.e. creates a small sample of a device that is representative of the whole device, such that the ratio of the quiescent current of the device to the quiescent current of the sample exhibits a linear relationship to the ratio of the component count of the device to the component count of the sample.

Leakage tracking device sample for IDDQ measurement and defect resolution

A Defect Insertion Testability Mode for IDDQ Testing to detect defects in a semiconductor device and for accuracy correction during testing. In one embodiment of the present invention a screen condition and a known defect current are selected for the device under test (DUT). The DUT is screened without a known defect current being inserted and then is screened again with a known defect current inserted. The results of screening the DUT with and without the known defect current are then compared and the screen condition is adjusted based upon this comparison in order to increase the accuracy of the IDDQ test.

Defect insertion testability mode for IDDQ testing methods

Cascode coupled magnetic field effect transistors used to measure magnetic field. The disclosed cascode coupled MagFET circuit includes cascode coupled transistors used to equalize the voltage at the drains of the MagFET resulting in a differential Hall current. The cascode devices are biased at a state of very weak inversion to maximize input impedance. The differential currents are amplified with an active current mirror load coupled to the cascode configured devices. A comparator is used to sense the differential currents. The reference voltages used to bias the MagFET and the cascode coupled devices are generated with a bias network including a MagFET precisely matched with the MagFET used to measure the magnetic field such that the magnetic field measuring circuit is exceptionally immune to variations in process, temperature and supply voltage.

Method and apparatus with cascode biasing magneto field effect

A circuit including daisy chain coupled triple drain magneto field effect transistors (MagFETs) for measuring magnetic field. The disclosed method and apparatus describe multiple MagFETs coupled together to accumulate voltage differentials generated in response to magnetic field. A lateral drain of a first triple drain MagFET is used to bias the gate of a second triple drain MagFET. The center drains and sources of each MagFET are biased with well matched current sources which permit the center drains and sources of each MagFET to float to a corresponding voltage biasing each triple drain MagFET near threshold. With the gate of each MagFET biased by a lateral drain of a prior MagFET, and with the source of each MagFET permitted to float to approximately a threshold voltage less than the corresponding gate voltage, the generated voltage differentials by each MagFET are accumulated thereby resulting in increased sensitivity to magnetic field. In addition, with the increased sensitivity, each MagFET is permitted to operate in a lower magnetic flux region resulting in improved overall linearity of differential voltage versus magnetic flux with the present invention.

Method and apparatus coupling together magneto field effect transistors

A triple drain magnetic field effect transistor (MagFET) for measuring magnetic field. The disclosed MagFET has a gate, a source, a center drain and two lateral drains and generates an increased Hall voltage between the two lateral drains. The MagFET provides a high conductivity channel disposed between the center drain and the source to allow a high sense current to flow. The relationship between the sense current and the background carrier concentration of the lateral drains of the transistor are effectively reduced or decoupled in order to provide the increased Hall voltage between the lateral drains in response to a magnetic field. The sense current is decoupled from the background carrier concentration of the lateral drains of the transistor by suppressing the threshold adjust ion implantation step of the high conductivity channel such that when measuring magnetic field, the carrier concentration of the high conductivity channel is greater than the carrier concentration of the regions of the two lateral drains of the MagFET.

Triple drain magneto field effect transistor with high conductivity

A method for detecting defects in a semiconductor device using an IDDQ testing technique that is not dependent upon the background leakage current for defect resolution. One embodiment of the present invention utilizes the dependence of the background leakage current on temperature and/or voltage to zero out the background leakage in determining the defect current of a device.

Method for testing a semiconductor device by measuring quiescent

A differential voltage memory apparatus is provided which includes one or more preliminary stages of differential amplifiers which operate prior to triggering of a final stage of differential amplifiers. The preliminary stages of differential amplifiers include cross-coupled inverters that are closely coupled to bit lines connected to memory cells of the memory apparatus. The final stage of sense amplifiers include cross-coupled inverters which are, in use, substantially decoupled from the bit lines of the memory cells. The preliminary sense amplifiers are activated shortly after activation of corresponding memory cells and provide an initial stage of amplification of a voltage differential generated by the memory cells. The final stage sense amplifiers are triggered after a suitable time delay guaranteeing that a sufficient minimum voltage differential has been generated. The preliminary sense amplifier stages, which are closely coupled to the bit lines and are thereby subject to heavy capacitive loading, provide an initial stage of amplification which is substantially immune from noise effects, such as effects caused by alpha strikes and the like. The final stage of sense amplifiers, which are substantially decoupled from the capacitive bit lines, coupled to quickly amplify the voltage differential to opposing rail voltages. The method and apparatus embodiments are described.

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Phoenix, AZ, United States of America

Jeffrey C Kalb, Jr