Taiwan Semiconductor Manufacturing Comp. Ltd.

Jeff J Xu

Chih-Hao Chang

Clement Hsingjen Wann

Chih-Hsin Ko

Tsung-Lin Lee

Feng Yuan

Liang-Gi Yao

Da-Yuan Lee

Kuang-Yuan Hsu

Xiong-Fei Yu

Chun-Yuan Chou

Anthony Yen

Shinn-Sheng Yu

Ming-Feng Shieh

Chen-Yi Lee

Chun-Hu Cheng

Chih Chieh Yeh

Shao-Ming Yu

Chang-Yun Chang

Neng-Kuo Chen

Chien-Hsun Wang

Chih-Hsiang Chang

Ta-Ming Kuan

Chin-Hsiang Lin

Ziwei Fang

Pang-Yen Tsai

Chia-Cheng Chen

Chun-Hung Lee

Chi-Sheng Chang

Huicheng Chang

Chun Hsiung Tsai

Zhiqiang Wu

Chia-Ta Hsieh

Ming-Ching Chang

Tsz-Mei Kwok

Wen-Chin Lee

Chun-Feng Nieh

Yu-Hung Cheng

Cheng-Tung Lin

Yimin Huang

Min Cao

Hung-Ta Lin

Hsin-Chih Chen

Ming-Jie Huang

Chun-Pei Wu

Chia-Chi Chung

Hsiang-Yi Wang

Ying Zhang

Betty Hsieh

Chi Chieh Yeh

Chi Cheh Yeh

A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

Method for fabricating a strained structure and structure formed

A semiconductor device with a metal gate is disclosed. An exemplary semiconductor device with a metal gate includes a semiconductor substrate, source and drain features on the semiconductor substrate, a gate stack over the semiconductor substrate and disposed between the source and drain features. The gate stack includes a HK dielectric layer formed over the semiconductor substrate, a plurality of barrier layers of a metal compound formed on top of the HK dielectric layer, wherein each of the barrier layers has a different chemical composition; and a stack of metals gate layers deposited over the plurality of barrier layers.

Techniques providing metal gate devices with multiple barrier layers

Methods for fabricating FinFETs with enhanced performance are disclosed herein. An exemplary method includes forming a first fin and a second fin having a trench defined therebetween. The first fin and the second fin each include a first semiconductor layer disposed over a second semiconductor layer. An isolation feature is formed in the trench between the first fin and the second fin. A gate structure is formed over the isolation feature, a first region of the first fin, and a first region of the second fin. The gate structure is disposed between second regions of the first fin and between second regions of the second fin. After recessing the first fin and the second fin, a third semiconductor layer is formed over the first fin and the second fin. In some embodiments, the third semiconductor layer extends over the isolation feature and merges the first fin and the second fin.

Fin-like field effect transistor (FinFET) device and method of manufacturing same

An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

Integrated circuit transistor structure with high germanium concentration SiGe stressor

A semiconductor device includes a semiconductor substrate and two fin structures. Channels of the fin structures include a second semiconductor material portion over a first semiconductor material portion. Source and drain regions of the first fin structure include a third semiconductor material portion over the first semiconductor material portion. Source and drain regions of the second fin structure include the second semiconductor material portion over the first semiconductor material portion and a fourth semiconductor material portion over the second semiconductor material portion. The first, second, third, and fourth semiconductor material portions are different in composition from each other.

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary method includes providing a semiconductor substrate; forming a first fin structure and a second fin structure over the semiconductor substrate; forming a gate structure over a portion of the first and second fin structures, such that the gate structure traverses the first and second fin structures; epitaxially growing a first semiconductor material on exposed portions of the first and second fin structures, such that the exposed portions of the first and second fin structures are merged together; and epitaxially growing a second semiconductor material over the first semiconductor material.

A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor structure with a hydrogen fluoride (HF)-containing gas. A method of forming a semiconductor device includes forming a recess in a source/drain (S/D) region of a transistor. The method of forming further includes cleaning the recess with a HF-containing gas, the HF-containing gas having an oxide removing rate of about 2 nanometer/minute (nm/min) or less. The method of forming further includes epitaxially forming a strain structure in the recess after the cleaning the recess, the strain structure providing a strain to a channel region of the transistor.

Method of forming a semiconductor structure

A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer.

Growing community of inventors

Jhubei, Taiwan

Jeff J Xu