Intel Corporation

Jeen-Yuan Miin

Sridhar Lakshmanamurthy

Prashant R Chandra

Wilson Y Liao

Chen-Chi Kuo

Yim Pun

Jaroslaw Sydir

Raymond Ng

Pun Yim

In general, in one aspect, the disclosure describes a processor that includes an instruction store to store instructions of at least a portion of at least one program and multiple engines coupled to the shared instruction store. The engines provide multiple execution threads and include an instruction cache to cache a subset of the at least the portion of the at least one program from the instruction store, with different respective portions of the engine's instruction cache being allocated to different respective ones of the engine threads.

Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache

Thread-based engine cache partitioning

Methods, software and systems for handling parity errors in flow control channels are presented. A network processor is provided having a flow control message First In First Out (FIFO) buffer and wherein the FIFO buffer includes a parity field. The network processor is included as either or both of an Ingress network processor and an Egress network processor and is used within a CSIX system or an NPSI NPE system.

Method and apparatus to handle parity errors in flow control channels

According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly from a next processing element in the series.

Processing element with next and previous neighbor registers for direct data transfer

Growing community of inventors

Palo Alto, CA, United States of America

Jeen-Yuan Miin