Advanced Micro Devices Corporation

Spansion Llc.

Other

Fasl LLC

Cypress Semiconductor Corporation

Advance Micro Devices, Inc.

Advanced Micro Device, Inc.

Jean Yee-Mei Yang

Yider Wu

Mark T Ramsbey

Hidehiko Shiraiwa

Zhizheng Liu

Tazrien Kamal

Yu Nan Sun

Cyrus E Tabery

Hiroyuki Kinoshita

Yi He

Emmanuil Lingunis

Jeff P Erhardt

Ning Cheng

Rinji Sugino

Jaeyong Park

Cinti Xiaohua Chen

Weidong Qian

Ming-Sang Kwan

Emmanuel H Lingunis

Minh Van Ngo

Angela Tai Hui

Sameer S Haddad

Mark W Randolph

Jeffrey Allan Shields

Arvind Halliyal

Darlene G Hamilton

Timothy J Thurgate

Robert A Huertas

Kouros Ghandehari

Shankar Sinha

Wenmei Li

Harpreet Kaur Sachar

Pei-Yuan Gao

Edward Hsia

Phillip Lawrence Jones

Jiahua Huang

Michael Brennan

Fred T K Cheung

Amy C Tu

Yun Wu

Tyagamohan Gottipati

Bradley Marc Davis

Vidyut Gopal

Jeyong Park

Emmanuil Manos Lingunis

Weidon Qian

In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.

Dielectric extension to mitigate short channel effects

A memory device includes a group of memory cells formed on a substrate, each memory cell including a source region and a drain region formed in the substrate. The memory device also includes a protection layer formed on top surfaces of the source regions and the drain regions, and on side surfaces of the group of memory cells.

Memory device protection layer

Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.

Thin oxide dummy tiling as charge protection

The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows a first polysilicon layer to be selectively doped subsequent to deposition of the second polysilicon layer. The doping increases the conductivity of the first polysilicon layer which can achieve a more robust charging protection for multi-bit core array and a more uniform distribution of charge.

Using implanted poly-1 to improve charging protection in dual-poly process

The present invention, in one embodiment, relates to a process for fabricating a charge trapping dielectric flash memory device including steps of providing a semiconductor substrate having formed thereon a gate stack comprising a charge trapping dielectric charge storage layer and a control gate electrode overlying the charge trapping dielectric charge storage layer; forming an oxide layer over at least the gate stack; and depositing a spacer layer over the gate stack, wherein the depositing step deposits a spacer material having a reduced hydrogen content relative to a hydrogen content of a conventional spacer material.

Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device

The present invention pertains to utilizing a salicide in establishing alignment marks in semiconductor fabrication. A metal layer is formed over exposed portions of a silicon substrate as well as oxide areas formed over bitlines buried within the substrate. The metal layer is treated to react with the exposed portions of the silicon substrate to form salicided areas. The metal layer does not, however, react with the oxide areas. As such, salicided areas are formed adjacent to the oxide areas to provide an enhanced optical contrast when light is shined there-upon. In this manner, the alignment marks can be more readily 'seen'. The enhanced optical contrast thus allows the marks to continue to be seen as scaling occurs.

Alignment marks with salicided spacers between bitlines for alignment signal improvement

According to one embodiment, a memory structure comprises a substrate having a channel region situated between a source region and a drain region. The memory structure further comprises a gate layer formed over the channel region of the substrate, and a tunable interlayer dielectric formed over the gate layer and the substrate. The tunable interlayer dielectric has a transparent state and an opaque state, and comprises a matrix and electrically or magnetically tunable material situated within the matrix. During the transparent state, UV rays can pass through the tunable interlayer dielectric to the gate layer, e.g., to perform a UV erase operation. During the opaque state, UV rays are prevented from passing through the tunable interlayer dielectric to the gate layer, thereby protecting the gate layer against unwanted charge storage and extrinsic damage that may occur during various processes.

Memory structure having tunable interlayer dielectric and method for fabricating same

According to one exemplary embodiment, a method of fabricating memory array includes forming a number of hard mask lines and at least one dummy hard mask line on a layer of polysilicon, where the at least one dummy hard mask line is situated in a bitline contact region of the memory array. The method further includes removing the at least one dummy hard mask line. According to this embodiment, the method further includes forming a number of wordlines, where each of the wordlines is situated under one of the hard mask lines, and where the bitline contact region causes an irregularity in spacing of the wordlines. Two of the wordlines are situated adjacent to the bitline contact region such that the spacing between the two wordlines is substantially equal to a width of the bit line contact region.

Method for forming wordlines having irregular spacing in a memory array

Semiconductor devices with improved data retention are formed by depositing an undoped oxide liner on spaced apart transistors followed by in situ deposition of a BPSG layer. Embodiments include depositing an undoped silicon oxide liner derived from TEOS, as at a thickness of 400 &#x212b; to 600 &#x212b;, on transistors of a non-volatile semiconductor device, as by sub-atmospheric chemical vapor deposition, followed by depositing the BPSG layer in the same deposition chamber.

Undoped oxide liner/BPSG for improved data retention

The present invention pertains to implementing a dual poly process in forming a transistor based memory device. The process allows buried bitlines to be formed with less energy and to shallower depths than conventional bitlines to save resources and space, and to improve Vt roll-off. Oxide materials are also formed over the buried bitlines to improve (e.g., increase) a breakdown voltage between the bitlines and wordlines, thus allowing for greater discrimination between programming and erasing charges and more reliable resulting data storage. The process also facilitates a reduction in buried bitline width and thus allows bitlines to be formed closer together. As a result, more devices can be 'packed' within the same or a smaller area.

Bitline implant utilizing dual poly

A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate, a bottom dielectric, a charge storing layer, and a top dielectric in a stacked gate configuration. Silicided buried bitlines, which function as a source and a drain, are formed within the substrate. The silicided bitlines have a reduced resistance, which greatly reduces the number of bitline contacts necessary in an array of memory devices.

Memory device having silicided bitlines and method of forming the same

A non-volatile multi-bit memory cell is presented which comprises a source, a drain, a channel coupling the source and the drain, and a gate with a plurality of charge trapping regions located so that a trapped charge in each charge trapping region is enabled to affect the influence of the gate voltage on the flow of electrons in the channel. The charge trapping regions are in multiple layers of oxide/nitride/oxide and there can be multiple levels of charge trapping regions. Charges are stored in the nitride layers and isolated by the oxide layers.

Multi-bit silicon nitride charge-trapping non-volatile memory cell

A structure for protecting an NROM from induced charge damage during device fabrication is described. The structure provides a discharge path for charge accumulated on the polygate layer during fabrication while providing sufficient isolation to ensure normal circuit operation.

Method and structure for protecting NROM devices from induced charge damage during device fabrication

A method of fabricating a planar architecture charge trapping dielectric memory cell array with rectangular gates comprises fabricating a multi-layer charge trapping dielectric on the surface of a substrate. The layer adjacent to the substrate may be an oxide. A polysilicon layer is deposited over the charge trapping dielectric. A word line mask is applied over the polysilicon layer to mask linear word lines in a first direction and to expose trench regions there between and the trenches are etched to expose the charge trapping dielectric in the trench regions. A bit line mask is applied over the polysilicon layer to mask gates in a second direction perpendicular to the first direction and to expose bit line regions there between and the bit lines are etched to expose the oxide in the bit line regions. The bit lines are implanted and insulating spacers are fabricated on exposed sidewalls. The oxide is removed to expose the substrate between insulating spacers in the bit line regions and a conductor is fabricated thereon to enhance conductivity of each bit line.

Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

Methods are disclosed for fabricating dual bit SONOS flash memory cells, comprising forming polysilicon gate structures over an ONO layer, and doping source/drain regions of the substrate using the gate structures as an implant mask. Methods are also disclosed in which dielectric material is formed over and between the gate structures, and the wafer is planarized using an STI CMP process to remove dielectric material over the polysilicon gate structures.

Methods for fabricating and planarizing dual poly scalable SONOS flash memory

Growing community of inventors

Sunnyvale, CA, United States of America

Jean Yee-Mei Yang