Stmicroelectronics S.a.

Sgs-thomson Microelectronics S.a.

Bull S.a.

Sgs-thomas Microelectronics S.a.

Jean-Pierre Schoellkopf

Constantin Papadas

Richard P Fournel

Philippe Candelier

St&eacute;phane Hanriat

Joseph Borel

Sylvain Clerc

Francois Jacquet

Fady Abouzeid

Philippe Gayet

Hervé Jaouen

Fabian Firmin

Yann Boyer-Chammard

A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.

Flip-flop with single clock phase and with reduced dynamic power

The invention concerns a capacitor whereof one first electrode consists of a highly doped active region (D) of a semiconductor component (T) formed on one side of a surface of a semiconductor body, and whereof the second electrode consists of a conductive region (BR) coated with insulation (IL) formed beneath said active region and embedded in the semiconductor body.

Embedded capacitor

A semiconductor device includes several assembled integrated-circuit chips. A main integrated-circuit chip has at least one cavity in which electrical contacts are provided. A secondary integrated-circuit chip includes an edge which engages in the cavity of the main chip and has electrical contacts. When the secondary integrated-circuit chip is inserted into the cavity, the electrical contacts of the main chip and the electrical contacts of the secondary chip are placed so as to be in contact with one another.

Semiconductor device having several assembled integrated-circuit chips and method of assembling and electrically connecting the integrated-circuit chips

A one-time programmable, dual-bit memory device comprises one MOS storage transistor having a semiconductor substrate, first and second active regions formed under the surface of the substrate being separated by a part of the substrate forming a channel region, a gate formed on the surface of the said substrate in line with the channel region and whose respective distal ends are aligned with a part of the first active region and with a part of the second active region, respectively, which gate is permanently held at ground potential, and a gate oxide layer running between the gate and the surface of the substrate. The intact or broken down state between the gate and the first active region determines a stored value of a first bit, and the intact or broken down state between the gate and the second active region determines a stored value of a second bit.

One-time programmable memory device

An integrated circuit including an assembly of functional blocks and an interconnection network formed of at least N levels of conductive tracks separated by conductive via levels, the interconnection network including a power supply network comprising a first assembly of substantially parallel rails placed at the N-th track level, and a second assembly of substantially parallel rails placed at the (N&#x2212;1)-th track level under the first rail assembly, the rails of the first assembly being non-parallel to those of the second assembly, the power supply network further including, for each functional block, a third assembly of power supply rails placed at the (N&#x2212;2)-th track level above the elements of the considered block, and in which the rails of the second assembly form an acute angle smaller than 80&#xb0; with the rails of each third rail assembly.

Integrated circuit power supply network

A static memory device includes at least one memory cell with two cross-coupled CMOS inverters to be connected to first and second voltages. The substrate of the NMOS transistor of a first CMOS inverter is electrically insulated from the substrate of the NMOS transistor of the second CMOS inverter. The two substrates can be biased with the first voltage. A clear flash controller flash clears the cells for temporarily bring the bias of the substrate of the NMOS transistor of the first CMOS inverter to the second voltage.

SRAM memory device with flash clear and corresponding flash clear method

A semiconductor cell includes, within a substrate region, four active zones that are mutually laterally isolated, the first active zone to be connected to a first voltage, the second active zone, of an opposite type of conductivity to that of the first active zone, to be connected to a second voltage, the third and fourth active zones being mutually connected via an electrically conducting connection external to the substrate. The value of the binary data item is defined by an implantation of a chosen type in a predetermined part of the substrate region or in the third and fourth active zones.

Semiconductor memory device and corresponding programming method

A storage circuit using a dual-access memory includes means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access. At least two successive activations of the means control operations of the same type, either reading or writing operations.

Fast memory circuits and methods

A memory circuit with an error correcting system comprising an address bus (), an input data bus (), and an output data bus (), the circuit comprising a memory having an address bus (), a data bus () and an error correcting circuit comprising an encoder (). A first address register () is connected to the input address bus of the circuit for successively storing addresses corresponding to memory write operations only. A second data register () is connected to the input data bus of the circuit () for storing data transmitted to the encoder (). Circuits make it possible to introduce a one-cycle shift into the memory writes, without modifying reads, giving the encoder more time to compute error correcting codes.

Memory circuit comprising an error correcting code

A method of repairing a defect in an integrated electronic circuit caused by an incorrect lithographic mask includes the formation of an electrical isolation between two conducting parts of the circuit. The electrical isolation is obtained by at least partly filling, with an electrically insulating material, a volume hollowed out beforehand which would otherwise, and incorrectly, form an electrical connection between the two conducting parts. To do this, a mask having an aperture revealing the hollowed out volume is formed on the circuit, and the mask used to direct the filling of the electrically insulating material and correction of the lithography defined defect.

Method of repairing an integrated electronic circuit using a formed electrical isolation

A few times programmable (FTP) storage element is provided. The FTP storage element includes a set of N elementary memory units and multiple selection circuits. Each of the elementary memory units includes an address bus for connection to a main address bus and a data bus for connection to a main data bus. The selection circuits generate successive selection signals for successively selecting one of the elementary memory units in order to give exclusive access to the one selected elementary memory unit. The selection circuits operate so as to automatically select a next one of the elementary memory units upon detection of a predetermined condition. In preferred embodiments, each of the elementary memory units is programmable.

Storage element with a defined number of write cycles

An integrated static random access memory device includes four transistors and two resistors defining a memory cell. The four transistors are in a semiconductor substrate and are mutually interconnected by a local interconnect layer. The local interconnect layer is under a first metal level and a portion of the local interconnect layer defines above the substrate a base metal level. The two resistors extend in contact with a portion of the local interconnect layer between the base metal level and the first metal level.

Process for producing a resistor in an integrated circuit and corresponding integrated static random access memory device having four transistors and two resistors

The present invention relates to a latch including two first N-channel transistors connected to a low supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third P-channel transistors respectively coupling the two second transistors to a high supply potential and cross-controlled by the output terminals; and circuitry for maintaining the states of the output terminals when the first transistors are non-conductive.

Latch operating with a low swing clock signal

The present invention relates to a method of manufacturing an electrically programmable memory cell with a lateral floating gate with respect to the control gate, including the steps of forming an insulated control gate on an active area; forming a thin insulating layer around the control gate; successively depositing a thin layer of a conductive material and a layer of an insulating material; anisotropically etching the insulating material to form spacers of this material; and removing the portions of the thin conductive layer which are not coated with the spacers.

Electrically programmable memory cell

The present invention relates to a logic simulation method, in which a signal is switched between two logic states to simulate a transition of a real signal. The method comprises the step of inserting between the two logic states of the signal an intermediate state for a time interval indicative of the slope of the transition of the real signal.

Growing community of inventors

Grenoble, France

Jean-Pierre Schoellkopf