Commissariat a L'energie Atomique Et Aux Energies Alternatives

Centre National De La Recherche Scientifique

Commissariat a L'energie Atomique

Stmicroelectronics S.a.

Stmicroelectronics (Crolles 2) Sas

Soitec

Université Grenoble Alpes

Jean-Michel Hartmann

Abdelkader Aliane

Shay Reboh

Jean-Marc Fedeli

Jean-Louis Ouvrier-Buffet

Julie Widiez

Philippe Rodriguez

Yann Bogumilowicz

Willy Ludurczak

Zouhir Mehrez

Maud Vinet

Philippe Coronel

Oleg Kononchuk

Didier Landru

Frank Fournel

Karim Hassan

Perrine Batude

Ludovic Ecarnot

Romain Wacquez

Aomar Halimaoui

Alexei Tchelnokov

Vincent Reboud

Vincent Larrey

Thierry Baron

Mickaël Brun

Frédéric Mazen

Bertrand Szelag

Maryse Fournier

Frederic Mazen

Laurent J Vallier

Corrado Sciancalepore

Quentin Wilmart

François Rieutord

Pascal Besson

Benoit Sklenard

Vincent Calvo

Luc Andre

Virginie Loup

Hacile Kaya

Vincent Destefanis

Frédéric Milesi

Marie-Noelle Semeria

Houssein El Dirani

Leopold Virot

Etienne Eustache

Franck Bassani

Bassem Salem

Marie-Noëlle Semeria

Oleg Kononchuck

Pierre-Edouard Raynal

Mohamed-Aymen Mahjoub

Quentin Durlin

A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and—applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.

Process for hydrophilically bonding substrates

A method of polishing a semiconductor substrate, including: a) a step of multiple implantations of ions from an upper surface of the substrate, to modify the material of an upper portion of the substrate, the multiple implantation step comprising a plurality of successive implantations under different respective implantation orientations; and b) a step of selective removal of the upper portion of the substrate.

Semiconductor substrate polishing method

The fabrication of a first waveguide made of stoichiometric silicon nitride, of a second waveguide made of crystalline semiconductor material and of at least one active component optically coupled to the first waveguide via the second waveguide. The method includes: a) the formation of an aperture which passes through an encapsulation layer of the first waveguide and emerges in or on a substrate made of monocrystalline silicon, then b) the deposition by epitaxial growth of a crystalline seeding material inside the aperture until this crystalline seeding material forms a crystalline seed on a top face of the encapsulation layer, then c) a lateral epitaxy, of a crystalline semiconductor material from the crystalline seed formed to form a layer made of crystalline semiconductor material wherein the second waveguide is then produced.

Method for fabricating a photonic chip

An optoelectronic device includes an array of germanium-based photodiodes including a stack of semiconductor layers, made from germanium, trenches, and a passivation semiconductor layer, made from silicon. Each photodiode includes a silicon-germanium peripheral zone in the semiconductor portion formed through an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of the semiconductor portion.

Optoelectronic device having an array of germanium-based diodes with low dark current

A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650&#xb0; C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.

Low-temperature method for manufacturing a semiconductor-on-insulator substrate

A method of forming an opening in an insulating layer covering a semiconductor region including germanium, successively including: the forming of a first masking layer on the insulating layer; the forming on the first masking layer of a second masking layer including an opening; the etching of an opening in the first masking layer, in line with the opening of the second masking layer; the removal of the second masking layer by oxygen-based etching; and the forming of the opening of said insulating layer in line with the opening of the first masking layer, by fluorine-based etching.

Contacting area on germanium

A method for the nanoscale etching of a layer of GeSnon a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of GeSnusing a mixture comprising dichlorine (Cl) and dinitrogen (N) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of GeSnon the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of GeSnaccording to the etching method. A conduction channel made of GeSnfor a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of GeSn.

Method for the nanoscale etching of a germanium-tin alloy (GeSn) for a FET transistor

A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.

A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

Method for fabricating a monocrystalline structure

A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

Process for fabricating an array of germanium-based diodes with low dark current

A method for producing a waveguide including a germanium-based core and a cladding is provided, the method including a step of 'low temperature' depositing of a shell after forming the core by engraving, such that the deposition temperature is less than 780&#xb0; C., followed by a step of 'high temperature' depositing of a thick encapsulation layer. The shell and the encapsulation layer at least partially form the cladding of the waveguide. Optionally, a step of annealing under hydrogen at a &#x201c;low temperature&#x201d;, less than 750&#xb0; C., precedes the deposition of the shell. These &#x201c;low temperature&#x201d; annealing and depositing steps advantageously make it possible to avoid a post-engraving alteration of the free surfaces of the core during the forming of the cladding which is less germanium-rich.

Method for producing Ge-core based waveguides

The invention relates to a method for manufacturing a waveguide () comprising:

Waveguide manufacturing process

The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.

Process for producing a strained layer based on germanium-tin

First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.

Method for determining preferential deposition parameters for a thin layer of III-V material

The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.

Method of forming a strained silicon layer

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Meylan, France

Jean-Michel Hartmann